Shiro Sakiyama

13 papers Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2015 J jnl
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.
IEEE J. Solid State Circuits
Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2013 — conf
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.
ISSCC
Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2012 J jnl
A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koji Obata, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho
2010 — conf
A 69.8 dB SNDR 3
CICC
Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho
2010 J jnl
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback.
IEEE J. Solid State Circuits
Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho
2009 — conf
An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage.
ISSCC
Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho
2009 — conf
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
ASP-DAC
Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho
2008 J jnl
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System.
IEEE J. Solid State Circuits
Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho
2006 — conf
A 0.03mm
ISSCC
Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi, Makoto Hattori
2006 — conf
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution.
ISSCC
Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie
2005 J jnl
Mixed body bias techniques with fixed V
IEEE J. Solid State Circuits
Masaya Sumita, Shiro Sakiyama, Masayoshi Kinoshita, Yuta Araki, Yuichiro Ikeda, Kohei Fukuoka
1994 J jnl
Quantizer neuron model and neuroprocessor-named quantizer neuron chip.
IEEE J. Sel. Areas Commun.
Susumu Maruno, Toshiyuki Kohda, Hiroyuki Nakahira, Shiro Sakiyama, Masakatsu Maruyama
1990 J jnl
An image signal multiprocessor on a single chip.
IEEE J. Solid State Circuits
Masakatsu Maruyama, Hiroyuki Nakahira, Toshiyuki Araki, Shiro Sakiyama, Yoshitaka Kitao, Kunitoshi Aono, Haruyasu Yamada