Shiro Kamohara

14 papers Journal 5Unranked 9

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive. ICICDT Takumi Hasegawa, Yoshiki Yamamoto, Hideki Makiyama, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi
2015	—	`conf`	0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM. COOL Chips Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Hideki Makiyama, Takumi Hasegawa, Yoshiki Yamamoto, Shinobu Okanishi, Keiichi Maekawa, Naoki Banno, Makoto Miyamura, Koichiro Okamoto, Noriyuki Iguchi, Yasuhiro Ogasahara, Hidekazu Oda, Shiro Kamohara, Yasushi Yamagata, Nobuyuki Sugii, Hiromitsu Hada
2015	J	`jnl`	A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2015	J	`jnl`	A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM. IEEE Micro Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Hideki Makiyama, Takumi Hasegawa, Yoshiki Yamamoto, Shinobu Okanishi, Keiichi Maekawa, Naoki Banno, Makoto Miyamura, Koichiro Okamoto, Noriyuki Iguchi, Hidekazu Oda, Shiro Kamohara, Yasushi Yamagata, Nobuyuki Sugii, Hiromitsu Hada, Yasuhiro Ogasahara
2015	—	`conf`	Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process. ICICDT Duc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Xuan-Thuan Nguyen, Koichiro Ishibashi, Cong-Kha Pham
2014	—	`conf`	A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
2014	—	`conf`	A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2011	J	`jnl`	A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis. IEICE Trans. Electron. Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Hiroshi Uozaki, Isao Miyazaki, Shiro Kamohara, Yoshiyuki Kaneko, Kenji Kanamitsu
2007	J	`jnl`	Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node. IEEE J. Solid State Circuits Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya
2005	J	`jnl`	A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh
2004	—	`conf`	Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara
2002	—	`conf`	Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure. DFT Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto
2000	—	`conf`	Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters. ASP-DAC Mikako Miyama, Shiro Kamohara
1999	—	`conf`	Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design. CICC Mikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo