Shiro Dosho

39 papers Journal 25Unranked 14
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier.
IEEE Trans. Very Large Scale Integr. Syst.
Shiro Dosho, Ludovico Minati, Kazuki Maari, Shungo Ohkubo, Hiroyuki Ito
2024 J jnl
A neural network-based DPD coefficient determination for PA linearization in 5G and beyond-5G mmWave systems.
IEICE Electron. Express
Aravind Tharayil Narayanan, Ludovico Minati, Aran Hagihara, Jun Kobayashi, Toshihiro Shimura, Yoichi Kawano, Parthojit Chakraborty, Jim Bartels, Korkut Kaan Tokgoz, Shiro Dosho, Toshihide Suzuki, Hiroyuki Ito
2023 — conf
A Compact 0.9uW Direct-Conversion Frequency Analyzer for Speech Recognition with Wide-Range Q-Controlable Bandpass Rectifier.
VLSI Technology and Circuits
Shiro Dosho, Ludovico Minati, Kazuki Maari, Hiroyuki Ito
2023 — conf
Towards Digital Synthesis of Variable Q-Factor Direct-Conversion for Low-Power Edge Sensing.
SENSORS
Parthojit Chakraborty, Kazuki Maari, Jim Bartels, Alexandre Varieras, Aravind Tharayil Narayanan, Ludovico Minati, Shiro Dosho, Hiroyuki Ito
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2018 J jnl
A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers.
IEICE Electron. Express
Motohiro Takayasu, Shiro Dosho, Hiroyuki Ito, Daisuke Yamane, Toshifumi Konishi, Katsuyuki Machida, Noboru Ishihara, Kazuya Masu
2017 J jnl
A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique.
IEEE J. Solid State Circuits
Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2017 J jnl
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS.
IEICE Trans. Electron.
Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2017 — conf
Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.
ASP-DAC
Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2016 — conf
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter.
ESSCIRC
Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2016 — conf
An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.
VLSI Circuits
Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu
2015 J jnl
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan.
IEEE J. Solid State Circuits
Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
2015 J jnl
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.
IEEE J. Solid State Circuits
Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2014 — conf
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
ISSCC
Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
2013 — conf
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.
ISSCC
Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho
2013 J jnl
A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells.
IEICE Trans. Electron.
Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
2012 — conf
A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method.
VLSIC
Kazuo Matsukawa, Koji Obata, Yosuke Mitani, Shiro Dosho
2012 J jnl
A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koji Obata, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho
2012 J jnl
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects.
IEEE J. Solid State Circuits
Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho
2012 J jnl
Continuous-Time Delta-Sigma Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey.
IEICE Trans. Electron.
Shiro Dosho
2012 J jnl
Digital Calibration and Correction Methods for CMOS Analog-to-Digital Converters.
IEICE Trans. Electron.
Shiro Dosho
2012 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shiro Dosho
2012 J jnl
Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs.
IEEE J. Solid State Circuits
Shinichiro Uemura, Yukio Hiraoka, Takayuki Kai, Shiro Dosho
2011 — conf
A time-domain architecture and design method of high speed A-to-D converters with standard cells.
A-SSCC
Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
2011 J jnl
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration.
IEEE J. Solid State Circuits
Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa
2010 — conf
A 69.8 dB SNDR 3
CICC
Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho
2010 J jnl
A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator.
IEEE J. Solid State Circuits
Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, Akira Matsuzawa
2010 J jnl
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback.
IEEE J. Solid State Circuits
Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho
2009 J jnl
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration.
IEEE J. Solid State Circuits
Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa
2009 — conf
An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage.
ISSCC
Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho
2009 — conf
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
ASP-DAC
Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho
2008 J jnl
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System.
IEEE J. Solid State Circuits
Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho
2007 J jnl
An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter.
IEICE Trans. Electron.
Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie
2006 J jnl
A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit.
IEICE Trans. Electron.
Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa
2006 — conf
A 0.03mm
ISSCC
Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi, Makoto Hattori
2006 — conf
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution.
ISSCC
Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie
2005 J jnl
A background optimization method for PLL by measuring phase jitter performance.
IEEE J. Solid State Circuits
Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa
2002 J jnl
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process.
IEEE J. Solid State Circuits
Shiro Dosho, Takashi Morie, Hirokuni Fujiyama
2002 J jnl
Development of a CMOS Data Recovery PLL for DVD-ROMx14.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shiro Dosho, Naoshi Yanagisawa, Seiji Watanabe, Takahiro Bokui, Kazuhiko Nishikawa