Shireesh Kumar Rai

38 papers Journal 37Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
Chua-oscillator-driven modified RC4 stream cipher and its FPGA prototyping for secure communication.
Integr.
Navneet Sharma, Pravindra Kumar, Shireesh Kumar Rai, Sujit Kumar Patel
2026 J jnl
Compact design of MOSFET-only meminductor emulator and its application in chaos and neural spike generator.
Integr.
Anuj Kalra, Neeta Pandey, Shireesh Kumar Rai
2025 J jnl
Design and analysis of VDIBA-based chaotic oscillators and their applications in communication system.
Integr.
Kushal Kumar, Akshay Rana, Shireesh Kumar Rai, Bhawna Aggarwal
2025 J jnl
Design of a new compact multiplier-less memtranstor emulator and its application in neuromorphic and chaos generation.
Integr.
Manoj Kumar, Shireesh Kumar Rai, Bhawna Aggarwal, Maneesha Gupta
2025 J jnl
Electronically tunable CCCII and OTA-based fractional-order meminductor emulator and its application.
Turkish J. Electr. Eng. Comput. Sci.
Bhawna Aggarwal, Rupam Das, Shireesh Kumar Rai
2025 J jnl
Electronically tunable MOSFET-C only meminductor emulator and its application.
Integr.
Aashish Kumar, Shireesh Kumar Rai
2025 J jnl
Electronically tunable floating DXCCDITA-based universal memelement emulator and its applications.
Integr.
Shalini Gupta, Kunwar Singh, Shireesh Kumar Rai
2024 J jnl
A new DXCCDITA based meminductor emulator and its application in chaotic oscillator.
Turkish J. Electr. Eng. Comput. Sci.
Bhawna Aggarwal, Shireesh Kumar Rai, Harsh Jain
2024 J jnl
A single operational amplifier-based grounded meminductor mutators and their applications.
Turkish J. Electr. Eng. Comput. Sci.
Shalini Gupta, Kunwar Singh, Shireesh Kumar Rai
2024 J jnl
MOSFET-only Meminductor Emulator and its Application in Chaotic Oscillator.
Circuits Syst. Signal Process.
Aashish Kumar, Shireesh Kumar Rai
2024 J jnl
Meminductor emulators using off-the-shelf active blocks with application in chaotic oscillator.
Integr.
Shireesh Kumar Rai, Bhawna Aggarwal, Vikas Singroha
2023 J jnl
A Floating Decremental/ Incremental Meminductor Emulator Using Voltage Differencing Inverted Buffered Amplifier and Current Follower.
J. Circuits Syst. Comput.
Bhawna Aggarwal, Shireesh Kumar Rai, Akanksha Arora, Amaan Siddiqui, Rupam Das
2023 J jnl
A Fractional-Order Meminductor Emulator Using OTA and CDBA with Application in Adaptive Learning Circuit.
Wirel. Pers. Commun.
Anshul Gupta, Shireesh Kumar Rai, Maneesha Gupta
2023 J jnl
A New Generalized Approach for the Realization of Meminductor Emulator and Its Application.
Wirel. Pers. Commun.
Ansh Goel, Shireesh Kumar Rai, Bhawna Aggarwal
2023 J jnl
A Novel Method for Authentication Using Chaotic Behaviour of Chua's Oscillator in (n,k) Secret Shared Data Scheme for Secure Communication.
IEEE Trans. Circuits Syst. I Regul. Pap.
Navneet Sharma, Pravindra Kumar, Shireesh Kumar Rai
2023 J jnl
An Electronically Tunable Meminductor Emulator and Its Application in Chaotic Oscillator and Adaptive Learning Circuit.
J. Circuits Syst. Comput.
Nisha Yadav, Shireesh Kumar Rai, Rishikesh Pandey
2023 J jnl
Chua's Oscillator-Based RSA Algorithm With Authenticated Masked Public Key for Secure Communication.
IEEE Trans. Consumer Electron.
Navneet Sharma, Pravindra Kumar, Shireesh Kumar Rai
2023 J jnl
New Electronically Tunable Four-Quadrant Analog Multiplier Employing Single EXCCCII and Its Applications.
Wirel. Pers. Commun.
Rupam Das, Shireesh Kumar Rai
2023 J jnl
New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators.
Integr.
Bhawna Aggarwal, Shireesh Kumar Rai, Anant Sinha
2022 J jnl
A High-Order Temperature-Compensated Subthreshold Voltage Reference Using Channel Length Modulation Compensation Technique.
Wirel. Pers. Commun.
Arvind Thakur, Rishikesh Pandey, Shireesh Kumar Rai
2022 J jnl
A Sub-1-V CMOS Voltage Reference with High PSRR and High Accuracy.
J. Circuits Syst. Comput.
Arvind Thakur, Rishikesh Pandey, Shireesh Kumar Rai
2022 J jnl
New Meminductor Emulators Using Single Operational Amplifier and Their Application.
Circuits Syst. Signal Process.
Aneet Singh, Shireesh Kumar Rai
2022 J jnl
Wideband High Gain Active Feedback Transimpedance Amplifier.
Wirel. Pers. Commun.
Preeti Singh, Maneesha Gupta, Bhawna Aggarwal, Shireesh Kumar Rai
2021 J jnl
A Low Supply Voltage, Low Line Sensitivity and High PSRR Subthreshold CMOS Voltage Reference.
J. Circuits Syst. Comput.
Arvind Thakur, Rishikesh Pandey, Shireesh Kumar Rai
2021 J jnl
A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth.
Turkish J. Electr. Eng. Comput. Sci.
Shireesh Kumar Rai, Rishikesh Pandey, Bharat Garg, Sujit Kumar Patel
2021 J jnl
High Frequency Electronically Tunable Floating Memristor Emulators employing VDGA and Grounded Capacitor.
Wirel. Pers. Commun.
Nisha Yadav, Shireesh Kumar Rai, Rishikesh Pandey
2021 J jnl
High Transconductance Gain Current Differencing Transconductance Amplifiers Using a New Approach of g
Wirel. Pers. Commun.
Raviraj Kour, Rishikesh Pandey, Shireesh Kumar Rai
2021 J jnl
New Grounded and Floating Memristor-Less Meminductor Emulators Using VDTA and CDBA.
J. Circuits Syst. Comput.
Nisha Yadav, Shireesh Kumar Rai, Rishikesh Pandey
2021 J jnl
Novel Meminductor Emulators Using Operational Amplifiers and their Applications in Chaotic Oscillators.
J. Circuits Syst. Comput.
Aneet Singh, Shireesh Kumar Rai
2020 J jnl
A power and area efficient approximate carry skip adder for error resilient applications.
Turkish J. Electr. Eng. Comput. Sci.
Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai
2020 J jnl
An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic.
J. Electron. Test.
Sujit Kumar Patel, Bharat Garg, Shireesh Kumar Rai
2020 J jnl
Design of Current Differencing Transconductance Amplifier using a Novel Approach of Transconductance Boosting for High Frequency Applications.
J. Circuits Syst. Comput.
Shireesh Kumar Rai, Rishikesh Pandey, Bharat Garg
2020 J jnl
Low temperature coefficient and low line sensitivity subthreshold curvature-compensated voltage reference.
Int. J. Circuit Theory Appl.
Arvind Thakur, Rishikesh Pandey, Shireesh Kumar Rai
2020 J jnl
New Grounded and Floating Decremental/Incremental Memristor Emulators Based on CDTA and Its Application.
Wirel. Pers. Commun.
Suchitra Gupta, Shireesh Kumar Rai
2020 J jnl
New grounded and floating memristor emulators using OTA and CDBA.
Int. J. Circuit Theory Appl.
Nisha Yadav, Shireesh Kumar Rai, Rishikesh Pandey
2019 — conf
Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems.
iSES
Sujit Kumar Patel, Bharat Garg, Anurag Mahajan, Shireesh Kumar Rai
2019 J jnl
ES-COINA: A novel energy scalable quality-aware color interpolation architecture.
Microprocess. Microsystems
Bharat Garg, Shireesh Kumar Rai, Akash Puranik, G. K. Sharma
2018 J jnl
Comment: Multifunction Current Differencing Cascaded Transconductance Amplifier (MCDTA) and Its Application to Current-Mode Multiphase Sinusoidal Oscillator.
Wirel. Pers. Commun.
Shireesh Kumar Rai, Maneesha Gupta