Shinya Takamaeda-Yamazaki

82 papers A 1B 6C 1Misc 3Journal 35Unranked 36

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators. ESOP (2) Izumi Tanaka, Ken Sakayori, Shinya Takamaeda-Yamazaki, Naoki Kobayashi
2026	J	`jnl`	Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators. CoRR Izumi Tanaka, Ken Sakayori, Shinya Takamaeda-Yamazaki, Naoki Kobayashi
2025	—	`conf`	Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-Scalar Multiplication. COOL CHIPS Ayumi Ohno, Kotaro Shimamura, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-scalar Multiplication. CoRR Ayumi Ohno, Kotaro Shimamura, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination. ACM Trans. Reconfigurable Technol. Syst. Daichi Tokuda, Shinya Takamaeda-Yamazaki
2025	—	`conf`	Exploring the Versal AI Engine for 3D Gaussian Splatting. COOL CHIPS Kotaro Shimamura, Ayumi Ohno, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	Exploring the Versal AI Engine for 3D Gaussian Splatting. CoRR Kotaro Shimamura, Ayumi Ohno, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration. CoRR Tatsuya Kubo, Daichi Tokuda, Tomoya Nagatani, Masayuki Usui, Lei Qu, Ting Cao, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	Measuring Participant Contributions in Decentralized Federated Learning. CoRR Honoka Anada, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	PRIOT: Pruning-Based Integer-Only Transfer Learning for Embedded Systems. CoRR Honoka Anada, Sefutsu Ryu, Masayuki Usui, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	PRIOT: Pruning-Based Integer-Only Transfer Learning for Embedded Systems. IEEE Embed. Syst. Lett. Honoka Anada, Sefutsu Ryu, Masayuki Usui, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM. IEEE Comput. Archit. Lett. Tatsuya Kubo, Daichi Tokuda, Lei Qu, Ting Cao, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM. CoRR Tatsuya Kubo, Daichi Tokuda, Lei Qu, Ting Cao, Shinya Takamaeda-Yamazaki
2025	—	`conf`	RustSFQ: A Domain-Specific Language for SFQ Circuit Design. COOL CHIPS Mebuki Oishi, Sun Tanaka, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	RustSFQ: A Domain-Specific Language for SFQ Circuit Design. CoRR Mebuki Oishi, Sun Tanaka, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	Scalable Moment Propagation and Analysis of Variational Distributions for Practical Bayesian Deep Learning. IEEE Trans. Neural Networks Learn. Syst. Yuki Hirayama, Shinya Takamaeda-Yamazaki
2025	J	`jnl`	Uncertainty in Machine Learning and Future Computers. Computer Shinya Takamaeda-Yamazaki
2024	J	`jnl`	Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems. IEEE Micro Tatsuya Kubo, Shinya Takamaeda-Yamazaki
2024	—	`conf`	FS-Boost: Communication-Efficient Federated Subtree-Based Gradient Boosting Decision Trees. CCNC Kotaro Shimamura, Shinya Takamaeda-Yamazaki
2024	J	`jnl`	Federated Learning with Relative Fairness. CoRR Shogo Nakakita, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki, Masaaki Imaizumi
2024	B	`conf`	OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. ASPDAC Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
2024	A	`conf`	PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation. ICCAD Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
2024	J	`jnl`	PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation. CoRR Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
2023	—	`conf`	Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory. COOL CHIPS Tatsuya Kubo, Shinya Takamaeda-Yamazaki
2023	—	`conf`	GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation. MCSoC Yuki Hirayama, Kengo Suga, Shinya Takamaeda-Yamazaki
2023	J	`jnl`	HALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling. CoRR Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
2023	—	`conf`	High-Level Synthesis of Memory Systems for Decoupled Data Orchestration. ARC Masayuki Usui, Shinya Takamaeda-Yamazaki
2023	—	`conf`	MAO: Memory Architecture Obfuscation. MCSoC Sun Tanaka, Shinya Takamaeda-Yamazaki
2023	J	`jnl`	MITA: Multi-Input Adaptive Activation Function for Accurate Binary Neural Network Hardware. IEICE Trans. Inf. Syst. Peiqi Zhang, Shinya Takamaeda-Yamazaki
2023	J	`jnl`	OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. CoRR Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka
2023	—	`conf`	Poison Egg: Scrambling Federated Learning with Delayed Backdoor Attack. UbiSec Masayoshi Tsutsui, Tatsuya Kaneko, Shinya Takamaeda-Yamazaki
2023	—	`conf`	SPinS-FL: Communication-Efficient Federated Subnetwork Learning. CCNC Masayoshi Tsutsui, Shinya Takamaeda-Yamazaki
2022	—	`conf`	Accelerating Decision Tree Ensemble with Guided Branch Approximation. HEART Keisuke Kamahori, Shinya Takamaeda-Yamazaki
2022	—	`conf`	FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. FPT Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
2022	J	`jnl`	FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. CoRR Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
2022	J	`jnl`	MP-GELU Bayesian Neural Networks: Moment Propagation by GELU Nonlinearity. CoRR Yuki Hirayama, Shinya Takamaeda-Yamazaki
2022	B	`conf`	Model-based Federated Reinforcement Distillation. GLOBECOM Sefutsu Ryu, Shinya Takamaeda-Yamazaki
2022	—	`conf`	Multi-Input Adaptive Activation Function for Binary Neural Networks. CANDARW Peiqi Zhang, Shinya Takamaeda-Yamazaki
2021	J	`jnl`	A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2021	—	`conf`	ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design. ASAP Yoshiki Fujiwara, Shinya Takamaeda-Yamazaki
2021	B	`conf`	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. FPL Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
2021	J	`jnl`	An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. CoRR Nobuho Hashimoto, Shinya Takamaeda-Yamazaki
2021	J	`jnl`	STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2021	J	`jnl`	Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. IEEE Access Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura
2020	—	`conf`	7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2020	C	`conf`	A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
2020	—	`conf`	Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. ARC Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	—	`conf`	A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	—	`conf`	DeltaNet: Differential Binary Neural Network. ASAP Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	J	`jnl`	Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2019	J	`jnl`	FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2019	J	`jnl`	QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2018	J	`jnl`	A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. IEICE Trans. Inf. Syst. Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
2018	—	`conf`	Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2018	J	`jnl`	BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2018	—	`conf`	Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2018	J	`jnl`	Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
2018	—	`conf`	QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
2018	Misc	`conf`	Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai
2017	—	`conf`	A Time-Division Multiplexing Ising Machine on FPGAs. HEART Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	Accelerating deep learning by binarized hardware. APSIPA Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	Misc	`conf`	CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. FCCM Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima
2017	B	`conf`	FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
2017	—	`conf`	In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2017	—	`conf`	Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
2017	—	`conf`	Quantization Error-Based Regularization in Neural Networks. SGAI Conf. Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
2016	—	`conf`	CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing. CANDAR Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2016	—	`conf`	CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. CANDAR Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2016	J	`jnl`	Performance Optimization of Light-Field Applications on GPU. IEICE Trans. Inf. Syst. Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2016	—	`conf`	Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs. CANDAR Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2015	—	`conf`	A CGRA-Based Approach for Accelerating Convolutional Neural Networks. MCSoC Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
2015	—	`conf`	A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations. CANDAR Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima
2015	J	`jnl`	Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. IEICE Trans. Inf. Syst. Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
2015	—	`conf`	Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. ARC Shinya Takamaeda-Yamazaki
2015	J	`jnl`	Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs. IEICE Trans. Inf. Syst. Shinya Takamaeda-Yamazaki, Hiroshi Nakatsuka, Yuichiro Tanaka, Kenji Kise
2014	—	`conf`	A framework for efficient rapid prototyping by virtually enlarging FPGA resources. ReConFig Shinya Takamaeda-Yamazaki, Kenji Kise
2014	—	`conf`	Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. CANDAR Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima
2014	B	`conf`	Ultrasmall: The smallest MIPS soft processor. FPL Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise
2014	B	`conf`	flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. FPL Shinya Takamaeda-Yamazaki, Kenji Kise
2012	—	`conf`	ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. ARC Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise
2012	Misc	`conf`	Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations. ICNC Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise
2011	J	`jnl`	An FPGA-based scalable simulation accelerator for tile architectures. SIGARCH Comput. Archit. News Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, Kenji Kise