Shinya Honda

66 papers A* 1A 1B 1C 5Misc 3Journal 32Unranked 22
YearRankTypeTitle / Venue / Authors
2021 J jnl
TZmCFI: RTOS-Aware Control-Flow Integrity Using TrustZone for Armv8-M.
Int. J. Parallel Program.
Tomoaki Kawada, Shinya Honda, Yutaka Matsubara, Hiroaki Takada
2019 — conf
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System.
SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI
Toki Matsumoto, Yukikazu Nakamoto, Ryota Yamamoto, Shinya Honda, Kazutoshi Wakabayashi
2019 — conf
Performance Evaluation of CAESAR Authenticated Encryption on SROS2.
AICCC
Shu Takemoto, Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa, Shinya Honda, Ryo Kurachi
2019 — conf
Process monitoring of deep drawing using machine learning.
AIM
Tomohiro Tsuruya, Musashi Danseko, Katsuhiko Sasaki, Shinya Honda, Ryo Takeda
2018 C conf
Cost-Effective Redundancy Approach for Fail-Operational Autonomous Driving System.
ISORC
Tasuku Ishigooka, Shinya Honda, Hiroaki Takada
2018 — conf
Efficient Approach to Ensure Temporal Determinism in Automotive Control Systems.
ISED
Masataka Ogawa, Shinya Honda, Hiroaki Takada
2017 J jnl
In-vehicle Distributed Time-critical Data Stream Management System for Advanced Driver Assistance.
J. Inf. Process.
Akihiro Yamaguchi, Yousuke Watanabe, Kenya Sato, Yukikazu Nakamoto, Yoshiharu Ishikawa, Shinya Honda, Hiroaki Takada
2017 Misc conf
Test Program Generator for AUTOSAR OS.
EDCC
Kazuto Shigihara, Shinya Honda, Hiroaki Takada
2016 — conf
A Map Database System for Route Navigation with Multiple Transit Points and Destination Points.
IIAI-AAI
Kunihiko Kaneko, Shinya Honda
2015 A* conf
AEDSMS: Automotive Embedded Data Stream Management System.
ICDE
Akihiro Yamaguchi, Yukikazu Nakamoto, Kenya Sato, Yoshiharu Ishikawa, Yousuke Watanabe, Shinya Honda, Hiroaki Takada
2015 — conf
Adaptive control for vibration suppression by using self-organization map.
ASCC
Shinya Honda, Yoshihiro Narita, Naohiro Kida
2015 J jnl
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip.
Inf. Media Technol.
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro
2015 J jnl
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip.
IPSJ Trans. Syst. LSI Des. Methodol.
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro
2015 J jnl
System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler.
J. Inf. Process.
Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro
2014 J jnl
A Case Study of FPGA Blokus Duo Solver by System-Level Design.
SIGARCH Comput. Archit. News
Yuki Ando, Masataka Ogawa, Yuya Mizoguchi, Kouta Kumagai, Miaw Torng-Der, Shinya Honda
2014 Misc conf
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs.
FCCM
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2014 J jnl
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs.
Inf. Media Technol.
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2014 J jnl
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs.
IPSJ Trans. Syst. LSI Des. Methodol.
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2014 — conf
Real-Time-Aware Embedded DSMS Applicable to Advanced Driver Assistance Systems.
SRDS Workshops
Satoshi Katsunuma, Shinya Honda, Kenya Sato, Yousuke Watanabe, Yukikazu Nakamoto, Hiroaki Takada
2014 — conf
Toward Data-Centric Software Architecture for Automotive Systems - Embedded Data Stream Processing Approach.
UIC/ATC/ScalCom
Yukikazu Nakamoto, Akihiro Yamaguchi, Kenya Sato, Shinya Honda, Hiroaki Takada
2013 — conf
Android Platform Based on Vehicle Embedded Data Stream Processing.
UIC/ATC
Yukikazu Nakamoto, Masanori Okamoto, Mohanmed Bhuiya, Akihiro Yamaguchi, Kenya Sato, Shinya Honda, Hiroaki Takada
2013 — conf
Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration.
IESS
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2013 J jnl
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks.
Inf. Media Technol.
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2013 J jnl
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks.
IPSJ Trans. Syst. LSI Des. Methodol.
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2013 J jnl
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs.
Int. J. Reconfigurable Comput.
Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada
2013 J jnl
Reliable and Efficient Dual-OS Communications for Real-Time Embedded Virtualization.
Inf. Media Technol.
Daniel Sangorrín, Shinya Honda, Hiroaki Takada
2012 J jnl
A Fast Performance Estimation Framework for System-Level Design Space Exploration.
IPSJ Trans. Syst. LSI Des. Methodol.
Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2012 J jnl
A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs.
IEICE Trans. Inf. Syst.
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2012 C conf
An Open-Source Flexible Scheduling Simulator for Real-Time Applications.
ISORC
Yutaka Matsubara, Yasumasa Sano, Shinya Honda, Hiroaki Takada
2012 J jnl
Comparison of Preemption Schemes for Partially Reconfigurable FPGAs.
IEEE Embed. Syst. Lett.
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
2012 J jnl
Convergent evolution in structural elements of proteins investigated using cross profile analysis.
BMC Bioinform.
Kentaro Tomii, Yoshito Sawada, Shinya Honda
2012 J jnl
Integrated Scheduling for a Reliable Dual-OS Monitor.
Inf. Media Technol.
Daniel Sangorrín, Shinya Honda, Hiroaki Takada
2012 — conf
Reliable Device Sharing Mechanisms for Dual-OS Embedded Trusted Computing.
TRUST
Daniel Sangorrín, Shinya Honda, Hiroaki Takada
2012 — conf
Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis.
HPCC-ICESS
Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2011 — conf
Fast design space exploration for mixed hardware-software embedded systems.
ISOCC
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2011 — conf
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems.
ISOCC
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
2011 — conf
Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs.
ReConFig
Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
2010 B conf
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems.
FPL
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2010 — conf
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis.
DELTA
Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2010 J jnl
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2010 C conf
Automatic communication synthesis with hardware sharing for design space exploration.
ISCAS
Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2010 J jnl
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation.
Inf. Media Technol.
Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2010 J jnl
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation.
IPSJ Trans. Syst. LSI Des. Methodol.
Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2010 J jnl
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2009 J jnl
ProSeg: a database of local structures of protein segments.
J. Comput. Aided Mol. Des.
Yoshito Sawada, Shinya Honda
2009 J jnl
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis.
Inf. Media Technol.
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2009 J jnl
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis.
J. Inf. Process.
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2008 C conf
CHStone: A benchmark program suite for practical C-based high-level synthesis.
ISCAS
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
2008 J jnl
Embedded System Covalidation with RTOS Model and FPGA.
Inf. Media Technol.
Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada
2008 J jnl
Embedded System Covalidation with RTOS Model and FPGA.
IPSJ Trans. Syst. LSI Des. Methodol.
Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada
2008 J jnl
Free Energy Landscape Analysis System Based on Parallel Molecular Dynamics Simulation.
Inf. Media Technol.
Masakazu Sekijima, Junta Doi, Shinya Honda, Tamotsu Noguchi, Shigenori Shimizu, Yutaka Akiyama
2007 — conf
A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems.
ICESS
Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2007 — conf
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.
ICESS
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
2007 — conf
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis.
ACM Great Lakes Symposium on VLSI
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
2007 J jnl
Function Call Optimization for Efficient Behavioral Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2007 J jnl
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii
2007 J jnl
Practice and analysis of an extension course for training trainers of embedded software.
SIGBED Rev.
Masaki Yamamoto, Shinya Honda, Hiroaki Takada, Kiyoshi Agusa, Hiroyuki Tomiyama, Kenji Mase, Nobuo Kawaguchi, Nobuyuki Kaneko
2007 — conf
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip.
ASP-DAC
Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2006 C conf
Function Call Optimization in Behavioral Synthesis.
DSD
Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2005 J jnl
An RTOS-Based Design and Validation Methodology for Embedded Systems.
IEICE Trans. Inf. Syst.
Hiroyuki Tomiyama, Shin-ichiro Chikada, Shinya Honda, Hiroaki Takada
2005 — conf
Cosimulation of ITRON-based embedded software with SystemC.
HLDVT
Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
2005 J jnl
NEXCESS: Nagoya university extension courses for embedded software specialists.
SIGBED Rev.
Masaki Yamamoto, Hiroyuki Tomiyama, Hiroaki Takada, Kiyoshi Agusa, Kenji Mase, Nobuo Kawaguchi, Shinya Honda, Nobuyuki Kaneko
2004 Misc conf
RTOS-centric hardware/software cosimulator for embedded system design.
CODES+ISSS
Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada
2003 — ch.
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device.
Embedded Software for SoC
Shinya Honda, Hiroaki Takada
2003 A conf
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device.
DATE
Shinya Honda, Hiroaki Takada
2003 — conf
Hardware/Software Co-Configuration for Multiprocessor SoPC.
WSTFES
Hiroaki Takada, Shinya Honda, Reiji Nishiyama, Hiroshi Yuyama