Shinobu Miwa

55 papers A* 1A 2B 3C 5Misc 2Journal 20Unranked 22
YearRankTypeTitle / Venue / Authors
2026 J jnl
A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units.
Integr.
Chenlin Shi, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda, Shinobu Miwa
2026 — conf
Combining System- and User-Level Approaches to Improving Energy Efficiency in GPU-Based Supercomputers.
SCA/HPC Asia Workshops
Kohei Yoshida, Hayato Yamaki, Hiroki Honda, Kento Sato, Shinobu Miwa
2026 J jnl
Feedback-Based Dynamic Traffic Balancing for Multipath Routing in ISP Networks.
IEICE Trans. Inf. Syst.
Sho Sato, Shinobu Miwa, Hiroki Honda, Hayato Yamaki
2026 — conf
Towards Unified Acceleration: Weight-Stationary GEMM on HPC-oriented Elastic CGRAs.
SCA/HPC Asia
Chenlin Shi, Boma Anantasatya Adhi, Lin Teng, Jiaheng Liu, Shinobu Miwa, Kentaro Sano
2025 C conf
Analysis of MPI Parallel Code Generated by GPT-4o.
ISC
Rin Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda
2025 — conf
CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors.
ASP-DAC
Shinobu Miwa, Eiichiro Sekikawa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
2025 J jnl
VAHRM: Variation-Aware Resource Management in Heterogeneous Supercomputing Systems.
IEEE Trans. Parallel Distributed Syst.
Kohei Yoshida, Ryuichi Sakamoto, Kento Sato, Abhinav Bhatele, Hayato Yamaki, Hiroki Honda, Shinobu Miwa
2024 J jnl
Analyzing the impact of CUDA versions on GPU applications.
Parallel Comput.
Kohei Yoshida, Shinobu Miwa, Hayato Yamaki, Hiroki Honda
2024 J jnl
CNFET-OCL: Open-Source Cell Libraries for Advanced CNFET Technologies.
IEEE Access
Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
2024 — conf
Evaluating MPI Performance on SGX and Gramine.
CLUSTER Workshops
Kota Shimojima, Shinobu Miwa, Hayato Yamaki, Hiroki Honda
2024 — conf
Post-Route Power Estimation: A Case Study of RIKEN-CGRA.
CLUSTER Workshops
Chenlin Shi, Boma A. Adhi, Shinobu Miwa, Kentaro Sano
2024 — conf
Power-Efficiency Variation on A64FX Supercomputers and its Application to System Operation.
CLUSTER Workshops
Tomoya Kusaba, Yusuke Awaki, Kohei Yoshida, Shinobu Miwa, Hayato Yamaki, Toshihiro Hanawa, Hiroki Honda
2023 — conf
Analyzing the Performance Impact of HPC Workloads with Gramine+SGX on 3rd Generation Xeon Scalable Processors.
SC Workshops
Shinobu Miwa, Shin'ichiro Matsuo
2023 — conf
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology.
ASP-DAC
Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda
2022 B conf
Analyzing Performance and Power-Efficiency Variations among NVIDIA GPUs.
ICPP
Kohei Yoshida, Rio Sageyama, Shinobu Miwa, Hayato Yamaki, Hiroki Honda
2021 J jnl
PredCom: A Predictive Approach to Collecting Approximated Communication Traces.
IEEE Trans. Parallel Distributed Syst.
Shinobu Miwa, Ignacio Laguna, Martin Schulz
2020 J jnl
Evaluating architecture-level optimization in packet processing caches.
Comput. Networks
Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda
2020 J jnl
Footprint-Based DIMM Hotplug.
IEEE Trans. Computers
Shinobu Miwa, Masaya Ishihara, Hayato Yamaki, Hiroki Honda, Martin Schulz
2020 J jnl
RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache.
IEICE Trans. Inf. Syst.
Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda
2019 Misc conf
Evaluating the Impact of Energy Efficient Networks on HPC Workloads.
HiPC
Giorgis Georgakoudis, Nikhil Jain, Takatsugu Ono, Koji Inoue, Shinobu Miwa, Abhinav Bhatele
2019 — conf
Functionally-Predefined Kernel: a Way to Reduce CNN Computation.
PACRIM
Yuta Inouchi, Hayato Yamaki, Shinobu Miwa, Tomoaki Tsumura
2019 — conf
Multi-Level Packet Processing Caches.
COOL CHIPS
Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda
2018 A* conf
Data prediction for response flows in packet processing cache.
DAC
Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda
2016 J jnl
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.
IEICE Trans. Inf. Syst.
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2016 — conf
Evaluation of Task Mapping on Multicore Neural Network Accelerators.
CANDAR
Satoshi Shindo, Momoka Ohba, Tomoaki Tsumura, Shinobu Miwa
2016 — conf
Initial Study of Reconfigurable Neural Network Accelerators.
CANDAR
Momoka Ohba, Satoshi Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, Hiroki Honda
2015 C conf
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.
ICCD
Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
2015 A conf
Profile-based power shifting in interconnection networks with on/off links.
SC
Shinobu Miwa, Hiroshi Nakamura
2015 C conf
Runtime multi-optimizations for energy efficient on-chip interconnections1.
ICCD
Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2014 J jnl
Area-Efficient Microarchitecture for Reinforcement of Turbo Mode.
IEICE Trans. Inf. Syst.
Shinobu Miwa, Takara Inoue, Hiroshi Nakamura
2014 — conf
Data-aware power management for periodic real-time systems with non-volatile memory.
NVMSA
Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu
2014 J jnl
Design Aid of Multi-core Embedded Systems with Energy Model.
Inf. Media Technol.
Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura
2014 J jnl
Evaluation of Core Hopping on POWER7.
SIGMETRICS Perform. Evaluation Rev.
Shinobu Miwa, Charles Lefurgy
2014 — conf
Normally-off computing project: Challenges and opportunities.
ASP-DAC
Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa
2014 J jnl
Performance estimation of high performance computing systems with Energy Efficient Ethernet technology.
Comput. Sci. Res. Dev.
Shinobu Miwa, Sho Aita, Hiroshi Nakamura
2013 A conf
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.
DATE
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2013 B conf
Integrating Multi-GPU Execution in an OpenACC Compiler.
ICPP
Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Naoya Maruyama
2013 B conf
McRouter: Multicast within a router for high performance network-on-chips.
PACT
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2013 C conf
Performance modeling for designing NoC-based multiprocessors.
RSP
Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura
2013 C conf
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping.
ICCD
Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2013 — conf
Predict-More Router: A Low Latency NoC Router with More Route Predictions.
IPDPS Workshops
Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
2012 — conf
A novel power-gating scheme utilizing data retentiveness on caches.
ACM Great Lakes Symposium on VLSI
Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
2012 — conf
Communication Library to Overlap Computation and Communication for OpenCL Application.
IPDPS Workshops
Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura
2012 — conf
Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.
ISQED
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
2012 J jnl
Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
2012 — conf
Stepwise sleep depth control for run-time leakage power saving.
ACM Great Lakes Symposium on VLSI
Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
2011 J jnl
A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth.
J. Comput. Sci. Technol.
Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita
2011 J jnl
Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis.
IEICE Trans. Inf. Syst.
Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
2010 — conf
An Effective Replacement Policy Focusing on Lifetime of a Cache Line.
CDES
Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo
2010 Misc conf
Parallelizing Hilbert-Huang Transform on a GPU.
ICNC
Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo
2009 J jnl
An Instruction Scheduler for Dynamic ALU Cascading Adoption.
Inf. Media Technol.
Jun Yao, Kosuke Ogata, Hajime Shimada, Shinobu Miwa, Hiroshi Nakashima, Shinji Tomita
2009 — conf
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor.
CDES
Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo
2008 J jnl
A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases.
IEICE Trans. Inf. Syst.
Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita
2008 — conf
Low-Complexity Bypass Network Using Small RAM.
CDES
Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita
2007 J jnl
Optimal pipeline depth with pipeline stage unification adoption.
SIGARCH Comput. Archit. News
Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita