Shinobu Fujita

36 papers A* 2A 5C 4Journal 9Unranked 16

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications. VLSI Circuits Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami
2017	—	`conf`	Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2017	J	`jnl`	Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
2017	J	`jnl`	Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani
2016	—	`conf`	7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
2016	J	`jnl`	High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code. CoRR Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda
2016	J	`jnl`	Physically Unclonable Function using Initial Waveform of Ring Oscillators. CoRR Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
2015	—	`conf`	7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
2015	C	`conf`	Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura
2014	—	`conf`	Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. VLSIC Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita
2014	—	`conf`	Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
2014	—	`conf`	Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". ASP-DAC Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
2013	A	`conf`	D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
2013	—	`conf`	Patient Context: A New Concept for Gap Model to Understand Patient Satisfaction. ICServ Shinobu Fujita, Kazuyoshi Hidaka
2012	—	`conf`	Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita
2011	J	`jnl`	Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini
2010	A*	`conf`	Detachable nano-carbon chip with ultra low power. DAC Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong
2010	A	`conf`	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
2010	C	`conf`	Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. ISCAS Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima
2009	A	`conf`	CMOS vs Nano: comrades or rivals? FPGA Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger
2009	A	`conf`	Nano-electronics challenge chip designers meet real nano-electronics in 2010s? DATE Shinobu Fujita
2009	C	`conf`	Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
2009	J	`jnl`	ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier. IEEE J. Solid State Circuits Bipul C. Paul, Shinobu Fujita, Masaki Okajima
2008	—	`conf`	1200μm ISSCC Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita
2008	A	`conf`	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. ICCAD Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini
2008	C	`conf`	ROM based logic (RBL) design: High-performance and low-power adders. ISCAS Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima
2007	J	`jnl`	3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
2007	—	`conf`	Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection. CICC Shinichi Yasuda, Shinobu Fujita
2007	—	`conf`	ProBoPortable: does the cellular phone software promote emergent division of labor in project-based learning? CSCL Toshio Mochizuki, Hiroshi Kato, Kazaru Yaegashi, Toshihisa Nishimori, Yusuke Nagamori, Shinobu Fujita
2007	J	`jnl`	Prospect of ballistic CNFET in high performance applications: Modeling and analysis. ACM J. Emerg. Technol. Comput. Syst. Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
2006	—	`conf`	3D on-chip networking technology based on post-silicon devices for future networks-on-chip. Nano-Net Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
2006	A*	`conf`	Modeling and analysis of circuit performance of ballistic CNFET. DAC Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee
2006	—	`conf`	Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon
2006	—	`conf`	Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. ISVLSI Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita
2005	—	`conf`	Physical random number generators for cryptographic application in mobile devices. ESSCIRC Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita
2004	J	`jnl`	Physical random number generator based on MOS structure after soft breakdown. IEEE J. Solid State Circuits Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita