Shinji Kimura - RankMe

113 papers A* 2A 6B 2C 16Misc 1Journal 49Unranked 37

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Prime Factorization Using Partially Constrained Multiple Quantum Annealing With Analytical and Pattern-Based Variable Reduction. IEEE Trans. Computers Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura, Takashi Sato
2026	J	`jnl`	TGSyn: Transformer Guided Topology-based Exact Synthesis for Majority-Inverter Graphs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xianliang Ge, Shinichi Nishizawa, Shinji Kimura
2025	—	`conf`	Exploring Training of Approximate CNNs using Straight-Through and Linear Regression-Based Gradient Estimation. SOCC Ke Ma, Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura
2025	—	`conf`	Learned Image Codec on FPGA: Algorithm, Architecture and System Design. ASP-DAC Heming Sun, Jing Wang, Silu Liu, Shinji Kimura, Masahiro Fujita
2025	J	`jnl`	Multithread Implementation of Open Source Library Characterizer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Nishizawa, Masahiro Matsuda, Shinji Kimura
2025	A	`conf`	SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction. ICCAD Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato
2025	J	`jnl`	SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction. CoRR Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato
2025	J	`jnl`	Standard Cell Structure and Diffusion Reordering for Block Area Reduction in Double Diffusion Break FinFET Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Nishizawa, Shinji Kimura
2024	J	`jnl`	Input Data Format for Sparse Matrix in Quantum Annealing Emulator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sohei Shimomai, Kei Ueda, Shinji Kimura
2023	—	`conf`	A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery. SOCC Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura
2023	—	`conf`	An 8-point Approximate DCT Design with Optimized Signed Digit Encoding. SOCC Zekun Wang, Shinichi Nishizawa, Shinji Kimura
2023	J	`jnl`	Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier. IEEE Trans. Circuits Syst. II Express Briefs Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura
2023	B	`conf`	Compressed Input Data Format of Quantum Annealing Emulator. DCC Sohei Shimomai, Kei Ueda, Shinji Kimura
2023	—	`conf`	Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks. SOCC Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura
2023	—	`conf`	Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction. SOCC Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura
2023	J	`jnl`	Theory and Application of Topology-Based Exact Synthesis for Majority-Inverter Graphs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xianliang Ge, Shinji Kimura
2022	—	`conf`	ApproxTorch: An Approximate Multiplier Evaluation Environment for CNNs based on Pytorch. ISOCC Ke Ma, Shinji Kimura
2022	J	`jnl`	Exploration of an Inflection Point of Ventilation Parameters with Anaerobic Threshold Using Strucchange. Sensors Takenori Aida, Akira Shionoya, Hirofumi Nonaka, Kouji Hayami, Hisashi Uchiyama, Masahiro Nagamori, Satoshi Ohhashi, Mai Kobayashi, Tsugumi Takayama, Shinji Kimura
2022	C	`conf`	Topology-Based Exact Synthesis for Majority Inverter Graph. ISCAS Xianliang Ge, Shinji Kimura
2021	—	`conf`	Energy-Efficient Approximate Floating-Point Multiplier Based on Radix-8 Booth Encoding. ASICON Rongyu Ding, Yi Guo, Heming Sun, Shinji Kimura
2020	C	`conf`	Accuracy-Configurable Low-Power Approximate Floating-Point Multiplier Based on Mantissa Bit Segmentation. TENCON Jie Li, Yi Guo, Shinji Kimura
2020	J	`jnl`	Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yi Guo, Heming Sun, Ping Lei, Shinji Kimura
2020	—	`conf`	Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules. ASP-DAC Yi Guo, Heming Sun, Shinji Kimura
2019	J	`jnl`	Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
2019	—	`conf`	Approximate Multiplier Using Reordered 4-2 Compressor with OR-based Error Compensation. ASICON Yufeng Xu, Yi Guo, Shinji Kimura
2019	J	`jnl`	Design of Low-Cost Approximate Multipliers Based on Probability-Driven Inexact Compressors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yi Guo, Heming Sun, Ping Lei, Shinji Kimura
2019	—	`conf`	Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors. SoCC Yi Guo, Heming Sun, Shinji Kimura
2018	—	`conf`	A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing. ICECS Xiaoting Sun, Yi Guo, Zhenhao Liu, Shinji Kimura
2018	J	`jnl`	A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. IEEE Trans. Circuits Syst. Video Technol. Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, Satoshi Goto
2018	C	`conf`	Design of Power and Area Efficient Lower-Part-OR Approximate Multiplier. TENCON Yi Guo, Heming Sun, Shinji Kimura
2018	C	`conf`	Embedded Frame Compression for Energy-Efficient Computer Vision Systems. ISCAS Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
2018	C	`conf`	Energy-Efficient and High Performance Approximate Multiplier Using Compressors Based on Input Reordering. TENCON Zhenhao Liu, Yi Guo, Xiaoting Sun, Shinji Kimura
2018	J	`jnl`	Lossy Compression for Embedded Computer Vision Systems. IEEE Access Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura, Satoshi Goto
2018	—	`conf`	Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. APCCAS Yi Guo, Heming Sun, Li Guo, Shinji Kimura
2018	—	`conf`	Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. ASP-DAC Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura
2018	—	`conf`	Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity. ASP-DAC Canran Jin, Heming Sun, Shinji Kimura
2018	C	`conf`	Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression. ISCAS Li Guo, Dajiang Zhou, Jinjia Zhou, Shinji Kimura
2018	J	`jnl`	Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging. IEEE Trans. Biomed. Circuits Syst. Aya Ibrahim, Shuping Zhang, Federico Angiolini, Marcel Arditi, Shinji Kimura, Satoshi Goto, Jean-Philippe Thiran, Giovanni De Micheli
2017	J	`jnl`	A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor. IEICE Trans. Electron. Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2017	C	`conf`	A low-cost approximate 32-point transform architecture. ISCAS Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita
2017	J	`jnl`	Accelerating HEVC Inter Prediction with Improved Merge Mode Handling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura
2017	J	`jnl`	An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. IEEE J. Solid State Circuits Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
2017	J	`jnl`	CNN-MERP: An FPGA-Based Memory-Efficient Reconfigurable Processor for Forward and Backward Propagation of Convolutional Neural Networks. CoRR Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura
2017	J	`jnl`	Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2017	C	`conf`	Effective write-reduction method for MLC non-volatile memory. ISCAS Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC. IEEE Trans. Multim. Heming Sun, Dajiang Zhou, Landan Hu, Shinji Kimura, Satoshi Goto
2017	—	`conf`	Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. MWSCAS Fan Yang, Minghao Lin, Heming Sun, Shinji Kimura
2016	—	`conf`	14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. ISSCC Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto
2016	J	`jnl`	A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Heming Sun, Dajiang Zhou, Shuping Zhang, Shinji Kimura
2016	C	`conf`	CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks. ICCD Xushen Han, Dajiang Zhou, Shihao Wang, Shinji Kimura
2016	—	`conf`	Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. ICME Workshops Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2016	J	`jnl`	Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems. CoRR Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2016	—	`conf`	Optimization of area and power in multi-mode power gating scheme for static memory elements. APCCAS Xing Su, Shinji Kimura
2016	C	`conf`	Power-efficient and slew-aware three dimensional gated clock tree synthesis. VLSI-SoC Minghao Lin, Heming Sun, Shinji Kimura
2015	—	`conf`	A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015	C	`conf`	An independent bandwidth reduction device for HEVC VLSI video system. ISCAS Jiayi Zhu, Li Guo, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2015	J	`jnl`	ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder. ICME Workshops Landan Hu, Heming Sun, Dajiang Zhou, Shinji Kimura
2015	J	`jnl`	Low-Power Motion Estimation Processor with 3D Stacked Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2015	C	`conf`	Merge mode based fast inter prediction for HEVC. VCIP Zhengxue Cheng, Heming Sun, Dajiang Zhou, Shinji Kimura
2014	C	`conf`	An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder. VCIP Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto
2014	J	`jnl`	Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2014	B	`conf`	Fast SAO estimation algorithm and its VLSI architecture. ICIP Jiayi Zhu, Dajiang Zhou, Shinji Kimura, Satoshi Goto
2013	J	`jnl`	An Exact Approach for GPC-Based Compressor Tree Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2013	—	`conf`	Controlling-value-based power gating considering controllability propagation and power-off probability. ASICON Zhe Du, Yu Jin, Shinji Kimura
2013	J	`jnl`	Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Jin, Zhe Du, Shinji Kimura
2013	—	`conf`	Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
2013	Misc	`conf`	Eyeglass-based hands-free videophone. ISWC Shinji Kimura, Masaaki Fukumoto, Tsutomu Horikoshi
2013	J	`jnl`	Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naoya Okada, Yuichi Nakamura, Shinji Kimura
2012	J	`jnl`	Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xin Man, Takashi Horiyama, Shinji Kimura
2012	J	`jnl`	On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Jin, Shinji Kimura
2011	—	`conf`	High-parallel LDPC decoder with power gating design. ASICON Ying Cui, Xiao Peng, Yu Jin, Peilin Liu, Shinji Kimura, Satoshi Goto
2011	J	`jnl`	Multi-Operand Adder Synthesis Targeting FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2011	—	`conf`	Multi-stage power gating based on controlling values of logic gates. ASICON Yu Jin, Shinji Kimura
2011	A	`conf`	Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ISLPED Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2010	—	`conf`	Multi-operand adder synthesis on FPGAs using generalized parallel counters. ASP-DAC Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2010	J	`jnl`	Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xin Man, Takashi Horiyama, Shinji Kimura
2009	—	`conf`	An objective and subjective evaluation of an autostereoscopic 3d display. CHI Extended Abstracts Masashi Tsuboi, Shinji Kimura, Tsutomu Horikoshi
2009	J	`jnl`	Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chengjie Zang, Shinji Kimura
2009	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinji Kimura
2009	J	`jnl`	Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. IPSJ Trans. Syst. LSI Des. Methodol. Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2009	J	`jnl`	Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lei Chen, Shinji Kimura
2008	J	`jnl`	Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yun Yang, Shinji Kimura
2008	J	`jnl`	Fine-Grained Power Gating Based on the Controlling Value of Logic Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura
2008	J	`jnl`	Issue Mechanism for Embedded Simultaneous Multithreading Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chengjie Zang, Shigeki Imai, Steven Frank, Shinji Kimura
2008	C	`conf`	Synthesis of parallel prefix adders considering switching activities. ICCD Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2008	J	`jnl`	The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yun Yang, Shinji Kimura
2006	J	`jnl`	Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura
2006	J	`jnl`	Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
2006	—	`conf`	FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2006	J	`jnl`	Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	Transition-based coverage estimation for symbolic model checking. ASP-DAC Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
2005	A	`conf`	A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection. IPDPS Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura
2005	C	`conf`	Extended abstract: transition traversal coverage estimation for symbolic model checking. MEMOCODE Xingwen Xu, Shinji Kimura, Kazunari Horikawa, Takehiko Tsuchiya
2005	—	`conf`	Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
2005	J	`jnl`	Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinji Kimura
2004	—	`conf`	Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	Minimization of fractional wordlength on fixed-point conversion for high-level synthesis. ASP-DAC Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura
2003	J	`jnl`	A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe
2002	A	`conf`	Folding of logic functions and its application to look up table compaction. ICCAD Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara
2002	J	`jnl`	Look Up Table Compaction Based on Folding of Logic Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe
2001	—	`conf`	A real-time 64-monosyllable recognition LSI with learning mechanism. ASP-DAC Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
2001	—	`conf`	Speech recognition chip for monosyllables. ASP-DAC Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
2000	—	`conf`	An application specific Java processor with reconfigurabilities. ASP-DAC Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe
2000	—	`conf`	Multi-clock path analysis using propositional satisfiability. ASP-DAC Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe
1998	A	`conf`	Waiting false path analysis of sequential logic circuits for performance optimization. ICCAD Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe
1997	—	`conf`	A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya
1995	A*	`conf`	Residue BDD and Its Application to the Verification of Arithmetic Circuits. DAC Shinji Kimura
1992	A	`conf`	Precise timing verification of logic circuits under combined delay model. ICCAD Shinji Kimura, Shigemi Kashima, Hiromasa Haneda
1990	C	`conf`	A parallel algorithm for constructing binary decision diagrams. ICCD Shinji Kimura, Edmund M. Clarke
1987	J	`jnl`	Description and verification of input constraints and input-output specifications of logic circuits. Syst. Comput. Jpn. Shinji Kimura, Shuzo Yajima
1982	A*	`conf`	An Interactive Simulation System for structured logic design - ISS. DAC Takeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima