Shinichi Nishizawa

49 papers A* 1A 2C 3Journal 24Unranked 19
YearRankTypeTitle / Venue / Authors
2026 J jnl
Entropy Improvement in Latch-Based True Random Number Generator Using Negative Bias Temperature Instability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ruilin Zhang, Ye Cao, Haochen Zhang, Quan Cheng, Shinichi Nishizawa, Kiichi Niitsu, Hirofumi Shinohara
2026 J jnl
Prime Factorization Using Partially Constrained Multiple Quantum Annealing With Analytical and Pattern-Based Variable Reduction.
IEEE Trans. Computers
Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura, Takashi Sato
2026 J jnl
TGSyn: Transformer Guided Topology-based Exact Synthesis for Majority-Inverter Graphs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Xianliang Ge, Shinichi Nishizawa, Shinji Kimura
2025 — conf
Exploring Training of Approximate CNNs using Straight-Through and Linear Regression-Based Gradient Estimation.
SOCC
Ke Ma, Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura
2025 J jnl
Multithread Implementation of Open Source Library Characterizer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Nishizawa, Masahiro Matsuda, Shinji Kimura
2025 A conf
SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction.
ICCAD
Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato
2025 J jnl
SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction.
CoRR
Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato
2025 J jnl
Standard Cell Structure and Diffusion Reordering for Block Area Reduction in Double Diffusion Break FinFET Process.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Nishizawa, Shinji Kimura
2024 J jnl
De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ruilin Zhang, Haochen Zhang, Xingyu Wang, Ziyang Ye, Kunyang Liu, Shinichi Nishizawa, Kiichi Niitsu, Hirofumi Shinohara
2024 J jnl
Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN).
IEEE Access
Thatree Mamee, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Takayasu Sakurai, Shinichi Nishizawa, Wataru Saito
2023 — conf
A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery.
SOCC
Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura
2023 — conf
An 8-point Approximate DCT Design with Optimized Signed Digit Encoding.
SOCC
Zekun Wang, Shinichi Nishizawa, Shinji Kimura
2023 J jnl
Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs
Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura
2023 — conf
Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks.
SOCC
Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura
2023 J jnl
IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control.
IEEE Access
Zaiqi Lou, Thatree Mamee, Katsuhiro Hata, Makoto Takamiya, Shinichi Nishizawa, Wataru Saito
2023 J jnl
Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Nishizawa, Toru Nakura
2023 — conf
Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction.
SOCC
Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura
2022 — conf
Density Aware Cell Library Design for Design-Technology Co-Optimization.
ISQED
Shinichi Nishizawa, Toru Nakura
2022 J jnl
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
2022 J jnl
Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuki Imai, Shinichi Nishizawa, Kazuhito Ito
2021 J jnl
Supplemental PDK for ASAP7 Using Synopsys Flow.
IPSJ Trans. Syst. LSI Des. Methodol.
Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera
2020 A conf
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing.
ICCAD
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera
2020 J jnl
Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement.
IPSJ Trans. Syst. LSI Des. Methodol.
Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi
2019 J jnl
Analog circuit design methodology utilizing a structure of thin BOX FDSOI.
IEICE Electron. Express
Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito
2019 C conf
Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement.
IOLTS
Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi
2019 — conf
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits.
ISQED
A. K. M. Mahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, Yoshinobu Ichida
2019 A* conf
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.
DAC
Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera
2019 — conf
Switching of 3300V Scaled IGBT by 5V Gate Drive.
ASICON
Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa
2018 J jnl
DC-bias-voltage dependence of degradation of aluminum electrolytic capacitors.
Microelectron. Reliab.
Kazunori Hasegawa, Kousuke Tsuzaki, Shinichi Nishizawa
2018 J jnl
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Nishizawa, Hidetoshi Onodera
2018 J jnl
ESR and capacitance monitoring of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier.
Microelectron. Reliab.
Kazunori Hasegawa, Shinichi Nishizawa, Ichiro Omura
2018 J jnl
Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa
2018 — conf
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment.
VLSI Circuits
Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai
2018 — conf
Process variation aware D-Flip-Flop design using regression analysis.
ISQED
Shinichi Nishizawa, Hidetoshi Onodera
2018 — conf
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately.
ESSDERC
Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai
2017 — conf
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).
ASICON
Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, Hiromichi Ohashi, Hiroshi Iwai
2017 — conf
Pin accessibility evaluating model for improving routability of VLSI designs.
SoCC
Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera
2016 J jnl
Design and Analysis of a New Evaluation Circuit for Capacitors Used in a High-Power Three-Phase Inverter.
IEEE Trans. Ind. Electron.
Kazunori Hasegawa, Ichiro Omura, Shinichi Nishizawa
2016 J jnl
Temperature rise measurement for power-loss comparison of an aluminum electrolytic capacitor between sinusoidal and square-wave current injections.
Microelectron. Reliab.
Kazunori Hasegawa, Kentaro Kozuma, Kousuke Tsuzaki, Ichiro Omura, Shinichi Nishizawa
2015 — conf
An impact of process variation on supply voltage dependence of logic path delay variation.
VLSI-DAT
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2015 J jnl
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell.
IPSJ Trans. Syst. LSI Des. Methodol.
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2014 — conf
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation.
SoCC
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2014 — conf
Variation-aware Flip-Flop energy optimization for ultra low voltage operation.
SoCC
Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2013 — conf
Analysis and comparison of XOR cell structures for low voltage circuit design.
ISQED
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2013 J jnl
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012 — conf
A Standard Cell Optimization Method for Near-Threshold Voltage Operations.
PATMOS
Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2012 C conf
A flexible structure of standard cell and its optimization method for near-threshold voltage operation.
ICCD
Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
2011 — conf
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation.
ISQED
Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
2009 C conf
An Efficient Hardware Accelerator for Power Grid Simulation.
ISCAS
Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui