Shing-Wu Tung

17 papers C 2Journal 4Unranked 11
YearRankTypeTitle / Venue / Authors
2013 C conf
A 42.5µW/MHz ultra-low power 32-bit microcontroller - SPARK.
ICICS
Wei-Xiang Tang, Shui-An Wen, Shing-Wu Tung, Keng-Yu Lin, Chun-Chih Chen, Ching-Lung Su
2013 — conf
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.
VLSI-DAT
Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai
2012 — conf
A power management technology for mobile embedded system.
VLSI-DAT
Shui-An Wen, Chun-Chin Chen, Shing-Wu Tung
2012 — conf
Low power and high performance 3-D multimedia platform.
Hot Chips Symposium
Po-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung
2011 C conf
Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology.
HPCC
Jen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng
2011 — conf
Low power design and dynamic power management system for VLIW DSP subsystem.
ISPACS
Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung
2003 — conf
An automatic interconnection rectification technique for SoC design integration.
ASP-DAC
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2003 J jnl
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2003 — conf
SoC design integration by using automatic interconnection rectification.
ISCAS (4)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2002 J jnl
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2002 J jnl
On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
An AVPG for SOC design verification with port order fault model.
ISCAS (5)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Asian Test Symposium
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
2001 — conf
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality.
ISQED
Chih-Yuan Chen, Shing-Wu Tung
2001 — conf
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model.
HLDVT
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
1998 J jnl
A Logical Fault Model for Library Coherence Checking.
J. Inf. Sci. Eng.
Shing-Wu Tung, Jing-Yang Jou
1998 — conf
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.
Asian Test Symposium
Shing-Wu Tung, Jing-Yang Jou