Shin-ya Abe

13 papers C 1Journal 10Unranked 2
YearRankTypeTitle / Venue / Authors
2015 J jnl
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2015 J jnl
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2015 J jnl
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.
Inf. Media Technol.
Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2014 — conf
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs.
APCCAS
Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2014 J jnl
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.
IPSJ Trans. Syst. LSI Des. Methodol.
Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2013 — conf
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages.
VLSI-DAT
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013 J jnl
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.
Inf. Media Technol.
Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2013 J jnl
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.
IPSJ Trans. Syst. LSI Des. Methodol.
Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2013 J jnl
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2012 C conf
An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures.
ISCAS
Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012 J jnl
Energy-efficient High-level Synthesis for HDR Architectures.
Inf. Media Technol.
Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012 J jnl
Energy-efficient High-level Synthesis for HDR Architectures.
IPSJ Trans. Syst. LSI Des. Methodol.
Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012 J jnl
MH
IEICE Electron. Express
Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa