Shin'ichiro Okazaki

28 papers A* 1A 1B 2Misc 5Journal 13Unranked 6
YearRankTypeTitle / Venue / Authors
2012 Misc conf
Efficient data transfer operations for a SIMD processor array system.
ICASSP
Hanno Lieske, Shorin Kyo, Shouhei Nomoto, Sunao Torii, Yuki Kobayashi, Yasuyuki Ninomiya, Shin'ichiro Okazaki
2011 — conf
A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems.
A-SSCC
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
2011 J jnl
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements.
J. Signal Process. Syst.
Shorin Kyo, Shin'ichiro Okazaki
2010 J jnl
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application.
Inf. Media Technol.
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
2010 J jnl
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application.
IPSJ Trans. Syst. LSI Des. Methodol.
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
2009 — conf
IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems.
Hot Chips Symposium
Shorin Kyo, Shouhei Nomoto, Takuya Koga, Hanno Lieske, Shin'ichiro Okazaki
2009 — conf
Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors.
ICDSC
Shorin Kyo, Shouhei Nomoto, Shin'ichiro Okazaki
2008 — conf
In-vehicle vision processors for driver assistance systems.
ASP-DAC
Shorin Kyo, Shin'ichiro Okazaki
2008 J jnl
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor.
IEICE Trans. Inf. Syst.
Kazuyuki Sakurai, Shorin Kyo, Shin'ichiro Okazaki
2007 A conf
A low-cost mixed-mode parallel processor architecture for embedded systems.
ICS
Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki
2007 J jnl
An Integrated Memory Array Processor for Embedded Image Recognition Systems.
IEEE Trans. Computers
Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai
2007 Misc conf
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor.
MVA
Kazuyuki Sakurai, Shorin Kyo, Shin'ichiro Okazaki
2005 A* conf
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems.
ISCA
Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai
2004 J jnl
A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications.
IEICE Trans. Inf. Syst.
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda
2003 J jnl
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements.
IEEE J. Solid State Circuits
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda
2001 — conf
IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements.
ICIP (3)
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki
1996 J jnl
A 3.84 gips integrated memory array processor.
Syst. Comput. Jpn.
Yoshihiro Fujita, Nobuyuki Yamashita, Tohru Kimura, Kazuyuki Nakamura, Shin'ichiro Okazaki
1996 B conf
An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications.
ICPR
Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki
1996 Misc conf
IMAP-VISION: An SIMD Processor with High-Speed On-chip Memory and Large Capacity External Memory.
MVA
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
1995 J jnl
A compact real-time vision system using integrated memory array processor architecture.
IEEE Trans. Circuits Syst. Video Technol.
Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita
1995 J jnl
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.
IEEE J. Solid State Circuits
Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina
1994 J jnl
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.
IEEE J. Solid State Circuits
Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina
1994 Misc conf
A Compact 30GIPS Real-Time Vision System RVS-2.
MVA
Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita
1994 J jnl
A real-time vision system using an integrated memory array processor prototype.
Mach. Vis. Appl.
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
1993 — conf
Dataflow Graph Optimization for Dataflow Architectures - A Dataflow Optimizing Compiler.
ICPP (2)
Sholin Kyo, Shin'ichiro Okazaki, Masanori Mizoguchi
1992 Misc conf
A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI.
MVA
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
1992 J jnl
Imap: Integrated Memory Array Processor.
J. Circuits Syst. Comput.
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
1988 B conf
Knowledge-Based Approach for Adaptive Recognition of Drawings.
Pattern Recognition
Shin'ichiro Okazaki, Yoshitake Tsuji