Shin'ichi Wakabayashi

63 papers A 1B 6C 11Misc 1Journal 15Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Introduction and Implementation of Mechanism for Preventing Recipient Unapproved Transactions to Ethereum Blockchain System. IEEE Access Chuki Hayama, Yoko Kamidoi, Masataka Kawasaki, Shin'ichi Wakabayashi
2024	—	`conf`	A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation. ISMVL Rie Kometani, Shinobu Nagayama, Martin Lukac, Masato Inagi, Shin'ichi Wakabayashi
2024	B	`conf`	Enhancing Security of Generalization Methods Based on m-Invariance for Dynamic Data Publication. COMPSAC Fusu Zhang, Yoko Kamidoi, Shin'ichi Wakabayashi
2023	J	`jnl`	Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection. IPSJ Trans. Syst. LSI Des. Methodol. Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
2022	B	`conf`	Introduction of a New Method for Preventing Recipient Unapproved Transactions to Bitcoin Wallet. COMPSAC Chuki Hayama, Yoko Kamidoi, Shin'ichi Wakabayashi
2021	J	`jnl`	A Protocol for Preventing Transaction Commitment Without Recipient's Authorization on Blockchain and It's Implementation. IEEE Access Yoko Kamidoi, Ryousuke Yamauchi, Shin'ichi Wakabayashi
2020	B	`conf`	A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid Clouds. COMPSAC Shun Kawamoto, Yoko Kamidoi, Shin'ichi Wakabayashi
2020	B	`conf`	A Verifiable Secret Sharing Scheme without Using Multi-Party Computations. COMPSAC Takumi Makino, Yoko Kamidoi, Shin'ichi Wakabayashi
2019	—	`conf`	A Protocol for Preventing Transaction Commitment without Recipient's Authorization on Blockchain. COMPSAC (1) Ryosuke Yamauchi, Yoko Kamidoi, Shin'ichi Wakabayashi
2018	—	`conf`	A Nearest Neighbor Search Engine Using Distance-Based Hashing. FPT Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2018	—	`conf`	An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing. DEXA (2) Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2018	C	`conf`	Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection. DSD Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
2016	—	`conf`	An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data. FPT Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2015	J	`jnl`	Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi
2014	J	`jnl`	An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. Inf. Media Technol. Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2014	J	`jnl`	An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. IPSJ Trans. Syst. LSI Des. Methodol. Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
2014	—	`conf`	An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
2013	C	`conf`	A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. DSD Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi
2013	C	`conf`	A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. DSD Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
2011	C	`conf`	A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations. DSD Satoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi
2011	B	`conf`	An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. FPL Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama
2010	—	`conf`	An FPGA-based text search engine for approximate regular expression matching. FPT Yuichiro Utan, Shin'ichi Wakabayashi, Shinobu Nagayama
2009	—	`conf`	A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set. ERSA Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama
2008	—	`conf`	A systolic regular expression pattern matching engine and its application to network intrusion detection. FPT Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama
2007	Misc	`conf`	A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. PDPTA Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama
2007	—	`conf`	A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation. FPT Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama
2006	—	`conf`	A Decision Method of Attribute Importance for Classification by Outlier Detection. ICDE Workshops Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
2006	—	`conf`	FPGA implementation of tabu search for the quadratic assignment problem. FPT Shin'ichi Wakabayashi, Yoshihiro Kimura, Shinobu Nagayama
2005	—	`conf`	A Clustering Method Using an Irregular Size Cell Graph. RIDE Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
2005	—	`conf`	An Algorithm for Computing Global-Based Outlier Degrees on Data Sets. ICDE Workshops Takeshi Fushimi, Yoko Kamidoi, Shin'ichi Wakabayashi
2005	—	`conf`	Feature Extraction of Clusters Based on FlexDice. ICDE Workshops Tomotake Nakamura, Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
2005	—	`conf`	Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs. FPT Shin'ichi Wakabayashi, Kenji Kikuchi
2004	B	`conf`	An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. FPL Shin'ichi Wakabayashi, Kenji Kikuchi
2002	J	`jnl`	A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem. Algorithmica Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
2002	J	`jnl`	A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide
2002	J	`jnl`	A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Syst. Comput. Jpn. Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide
2002	—	`conf`	A hierarchical standard cell placement method based on a new cluster placement model. APCCAS (1) Shin'ichi Wakabayashi, Nobuyuki Iwauchi, Hajime Kubota
2001	J	`jnl`	Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Syst. Comput. Jpn. Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
2000	C	`conf`	An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. ISCAS Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi
2000	—	`conf`	Genetic algorithm accelerator GAA-II. ASP-DAC Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno
2000	—	`conf`	Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi
1999	J	`jnl`	A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integr. Tetsushi Koide, Shin'ichi Wakabayashi
1999	—	`conf`	An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta
1999	—	`conf`	Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
1998	—	`conf`	A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC Tetsushi Koide, Shin'ichi Wakabayashi
1998	A	`conf`	Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide
1997	J	`jnl`	A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integr. Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida
1997	—	`conf`	Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
1996	J	`jnl`	A three-layer over-the-cell multi-channel router for a new cell model. Integr. Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1996	J	`jnl`	Pin assignment with global routing for VLSI building block layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1995	C	`conf`	A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
1995	—	`conf`	A new performance driven placement method with the Elmore delay model for row based VLSIs. ASP-DAC Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
1995	—	`conf`	A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1995	—	`conf`	A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1995	C	`conf`	An MCM Routing Algorithm Considering Crosstalk. ISCAS Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
1994	C	`conf`	A Floorplanning Method with Topological Constraint Manipulation. ISCAS Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1994	C	`conf`	A Systolic Graph Partitioning Algorithm for VLSI Design. ISCAS Shin'ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida
1994	C	`conf`	On Three-Way Graph Partitioning. ISCAS Yoko Kamidoi, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1993	—	`conf`	A new global routing algorithm for over-the-cell routing in standard cell layouts. EURO-DAC Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1993	C	`conf`	Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints. ISCAS Shin'ichi Wakabayashi, Hiroshi Kusumoto, Hideki Mishima, Tetsushi Koide, Noriyoshi Yoshida
1992	—	`conf`	An optimal channel pin assignment with multiple intervals for building block layout. EURO-DAC Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
1989	—	`conf`	Visualized and modeless programming environment for form manipulation language. VL Jun'ichi Miyao, Shin'ichi Wakabayashi, Noriyoshi Yoshida, Yasushi Ohtahara
1985	J	`jnl`	Design of hardware algorithms by recurrence relations. Syst. Comput. Jpn. Shin'ichi Wakabayashi, Tohru Kikuno, Noriyoshi Yoshida