Shimpei Sato - RankMe

56 papers A 6B 5C 2Misc 4Journal 16Unranked 23

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Application of 9-Channel Pseudo-Color Maps in Deep Learning for Intracranial Hemorrhage Detection. Multimodal Technol. Interact. Shimpei Sato, Daisuke Oura, Hiroyuki Sugimori
2025	—	`conf`	Data-Driven Feedforward Control for Suppressing Coupled Vibrations in Positioning Systems. ICM Shota Teramoto, Daigo Yamaguchi, Shimpei Sato, Yoshihiro Maeda
2025	J	`jnl`	Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs. CoRR Misaki Kida, Shimpei Sato
2024	—	`conf`	Direct Data-Driven Control-Based Additive Feedforward Compensation for Fast and Precise Positioning Control. AIM Daigo Yamaguchi, Shimpei Sato, Yoshihiro Maeda
2024	—	`conf`	On Relation Between Leakage-Free Condition and Differential Filtering Order in ETFE-Based Frequency Responce Function Estimation AIM Yoshihiro Maeda, Taishi Yazawa, Shimpei Sato, Wataru Hara
2023	A	`conf`	Humanoid Walking System with CNN-Based Uneven Terrain Recognition and Landing Control with Swing-Leg Velocity Constraints. IROS Shimpei Sato, Kunio Kojima, Naoki Hiraoka, Kei Okada, Masayuki Inaba
2023	A	`conf`	Whole-Body Torque Control Without Joint Position Control Using Vibration-Suppressed Friction Compensation for Bipedal Locomotion of Gear-Driven Torque Sensorless Humanoid. IROS Takuma Hiraoka, Shimpei Sato, Naoki Hiraoka, Annan Tang, Kunio Kojima, Kei Okada, Masayuki Inaba, Koji Kawasaki
2022	A	`conf`	Robust Humanoid Walking System Considering Recognized Terrain and Robots' Balance. IROS Shimpei Sato, Yuta Kojio, Yohei Kakiuchi, Kunio Kojima, Kei Okada, Masayuki Inaba
2022	—	`conf`	Trajectory Generation and Compensation for External Forces with a Leg-wheeled Robot Designed for Human Passengers. Humanoids Yohei Kakiuchi, Yuta Kojio, Noriaki Imaoka, Daiki Kusuyama, Shimpei Sato, Yutaro Matsuura, Takeshi Ando, Masayuki Inaba
2021	A	`conf`	Drop Prevention Control for Humanoid Robots Carrying Stacked Boxes. IROS Shimpei Sato, Yuta Kojio, Kunio Kojima, Fumihito Sugai, Yohei Kakiuchi, Kei Okada, Masayuki Inaba
2021	J	`jnl`	Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder. IEICE Trans. Inf. Syst. Naoto Soga, Shimpei Sato, Hiroki Nakahara
2021	J	`jnl`	Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs. IEICE Trans. Inf. Syst. Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2020	J	`jnl`	A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shimpei Sato, Kano Akagi, Atsushi Takahashi
2020	—	`conf`	A Table Look-Up Based Ternary Neural Network Processor. ISMVL Yuta Suzuki, Naoto Soga, Shimpei Sato, Hiroki Nakahara
2020	—	`conf`	Fast Monocular Depth Estimation on an FPGA. IPDPS Workshops Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2020	J	`jnl`	SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. IEICE Trans. Inf. Syst. Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
2020	Misc	`conf`	Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs. FCCM Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2019	J	`jnl`	A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
2019	C	`conf`	A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution. ISCAS Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
2019	A	`conf`	An FPGA-based Fine Tuning Accelerator for a Sparse CNN. FPGA Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
2019	B	`conf`	FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. FPL Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
2019	—	`conf`	FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. ReConFig Ryosuke Kuramochi, Masayuki Shimoda, Youki Sada, Shimpei Sato, Hiroki Nakahara
2019	J	`jnl`	GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. IEICE Trans. Inf. Syst. Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
2019	—	`conf`	Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. MCSoC Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2019	—	`conf`	Noise Convolutional Neural Networks and FPGA Implementation. ISMVL Atsuki Munakata, Hiroki Nakahara, Shimpei Sato
2019	J	`jnl`	Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. IEICE Trans. Inf. Syst. Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2018	B	`conf`	A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). FPL Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
2018	A	`conf`	A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA. FPGA Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
2018	—	`conf`	A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). HEART Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara
2018	—	`conf`	A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor. ISMVL Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
2018	J	`jnl`	A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA. IEICE Trans. Inf. Syst. Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
2018	—	`conf`	A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. FPT Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
2018	—	`conf`	An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network. FPT Akira Jinguji, Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
2018	J	`jnl`	An FPGA Realization of a Random Forest with IEICE Trans. Inf. Syst. Akira Jinguji, Shimpei Sato, Hiroki Nakahara
2018	J	`jnl`	ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment. IEICE Trans. Inf. Syst. Shimpei Sato, Ryohei Kobayashi, Kenji Kise
2018	J	`jnl`	BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
2018	B	`conf`	Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. FPL Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2018	—	`conf`	Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang
2018	—	`conf`	Power Efficient Object Detector with an Event-Driven Camera on an FPGA. HEART Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2017	B	`conf`	A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. FPL Hiroki Nakahara, Tomoya Fujii, Shimpei Sato
2017	—	`conf`	All binarized convolutional neural network and its implementation on an FPGA. FPT Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
2017	—	`conf`	An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA. FPT Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
2017	J	`jnl`	Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA. ACM Trans. Reconfigurable Technol. Syst. Thiem Van Chu, Shimpei Sato, Kenji Kise
2017	—	`conf`	In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
2015	—	`conf`	ArchHDL: A Novel Hardware RTL Design Environment in C++. ARC Shimpei Sato, Kenji Kise
2015	—	`conf`	Effective Parallel Simulation of ArchHDL under Manycore Environment. CANDAR Tomohiro Misono, Ryohei Kobayashi, Shimpei Sato, Kenji Kise
2015	Misc	`conf`	Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. FCCM Thiem Van Chu, Shimpei Sato, Kenji Kise
2015	—	`conf`	Exana: an execution-driven application analysis tool for assisting productive performance tuning. SEPS@SPLASH Yukinori Sato, Shimpei Sato, Toshio Endo
2015	—	`conf`	Investigating potential performance benefits of memory layout optimization based on roofline model. SEPS@SPLASH Shimpei Sato, Yukinori Sato, Toshio Endo
2015	B	`conf`	Ultra-fast NoC emulation on a single FPGA. FPL Thiem Van Chu, Shimpei Sato, Kenji Kise
2014	—	`conf`	KNoCEmu: High Speed FPGA Emulator for Kilo-node Scale NoCs. MCSoC Thiem Van Chu, Shimpei Sato, Kenji Kise
2013	J	`jnl`	The Ultrasmall soft processor. SIGARCH Comput. Archit. News Yuichiro Tanaka, Shimpei Sato, Kenji Kise
2010	Misc	`conf`	Pattern-Based Systematic Task Mapping for Many-Core Processors. ICNC Shintaro Sano, Masahiro Sano, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
2010	Misc	`conf`	Smart Core System for Dependable Many-Core Processor with Multifunction Routers. ICNC Shinya Takamaeda, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
2009	C	`conf`	A Study of an Infrastructure for Research and Development of Many-Core Processors. PDCAT Koh Uehara, Shimpei Sato, Takefumi Miyoshi, Kenji Kise
2009	J	`jnl`	SimCell: A Processor Simulator for Multi-Core Architecture Research. Inf. Media Technol. Shimpei Sato, Naoki Fujieda, Akira Moriya, Kenji Kise