Shimeng Yu

249 papers A* 7A 14B 2C 20Misc 2Journal 106Unranked 97
YearRankTypeTitle / Venue / Authors
2026 J jnl
3-D Ferroelectric NAND In-Storage Processing Architecture for Mass Spectrometry.
IEEE Des. Test
Po-Kai Hsu, Weihong Xu, Minji Shon, Zijian Zhao, Kai Ni, Tajana Rosing, Shimeng Yu
2026 J jnl
3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering.
ACM Trans. Design Autom. Electr. Syst.
Wei-Hsing Huang, Cheng-Jhih Shih, Jian-Wei Su, Samuel Wade Wang, Vaidehi Garg, Yuyao Kong, Jen-Chun Tien, Nealson Li, Arijit Raychowdhury, Meng-Fan Chang, Yingyan (Celine) Lin, Shimeng Yu
2026 J jnl
ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimization.
CoRR
Ming-Yen Lee, Shimeng Yu
2026 J jnl
HAVEN: High-Bandwidth Flash Augmented Vector Engine for Large-Scale Approximate Nearest-Neighbor Search Acceleration.
CoRR
Po-Kai Hsu, Weihong Xu, Qunyou Liu, Tajana Rosing, Shimeng Yu
2026 J jnl
Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache.
IEEE Trans. Computers
Faaiq G. Waqar, Jungyoun Kwak, Junmo Lee, Omkar Phadke, Minji Shon, MohammadHosein Gholamrezaei, Kevin Skadron, Shimeng Yu
2026 J jnl
Physics-informed AI Accelerated Retention Analysis of Ferroelectric Vertical NAND: From Day-Scale TCAD to Second-Scale Surrogate Model.
CoRR
Gyujun Jeong, Sungwon Cho, Minji Shon, Namhoon Kim, Woohyun Hwang, Kwangyou Seo, Suhwan Lim, Wanki Kim, Daewon Ha, Prasanna Venkatesan Ravindran, Kihang Youn, Ram Cherukuri, Yiyi Wang, Suman Datta, Asif Islam Khan, Shimeng Yu
2026 J jnl
Scalable Digital Compute-in-Memory Ising Machines for Robustness Verification of Binary Neural Networks.
CoRR
Madhav Vadlamani, Rahul Singh, Yuyao Kong, Zheng Zhang, Shimeng Yu
2026 J jnl
System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures.
CoRR
Kiseok Lee, Sungwon Cho, Seongkwang Lim, Suman Datta, Shimeng Yu
2026 Misc conf
ThermLeT: Transformer-Based Temperature Prediction for 2.5D Chiplet Architecture.
VLSID
Varun Darshana Parekh, Anusha Devulapally, Sivani Devarapalli, Cassius Henderson, Shimeng Yu, Vijaykrishnan Narayanan
2025 J jnl
3-D Digital Compute-in-Memory Benchmark With A5 CFET Technology: An Extension to Lookup-Table-Based Design.
IEEE Trans. Very Large Scale Integr. Syst.
Junmo Lee, Minji Shon, Faaiq G. Waqar, Shimeng Yu
2025 J jnl
3DGauCIM: Accelerating Static/Dynamic 3D Gaussian Splatting via Digital CIM for High Frame Rate Real-Time Edge Rendering.
CoRR
Wei-Hsing Huang, Cheng-Jhih Shih, Jian-Wei Su, Samuel Wade Wang, Vaidehi Garg, Yuyao Kong, Jen-Chun Tien, Nealson Li, Arijit Raychowdhury, Meng-Fan Chang, Yingyan Lin, Shimeng Yu
2025 J jnl
A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration.
CoRR
Wei-Hsing Huang, Janak Sharda, Cheng-Jhih Shih, Yuyao Kong, Faaiq Waqar, Pin-Jun Chen, Yingyan Lin, Shimeng Yu
2025 J jnl
An In-Situ Spatial-Temporal Sequence Detector for Neuromorphic Vision Sensor Empowered by High Density Vertical NAND Storage.
CoRR
Zijian Zhao, Varun Darshana Parekh, Po-Kai Hsu, Yixin Qin, Yiming Song, A. N. M. Nafiul Islam, Ningyuan Cao, Siddharth Joshi, Thomas Kämpfe, Moonyoung Jung, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Sourav Dutta, Abhronil Sengupta, Xiao Gong, Shimeng Yu, Vijaykrishnan Narayanan, Kai Ni
2025 — conf
Analog In-Memory-Compute with Multi-bit Silicon Ferro FinFET Array for Improved Energy and Area Efficiency.
IMW
Eknath Sarkar, Dyutimoy Chakraborty, Wei-Chun Wang, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Omkar Phadke, Chengyang Zhang, Emmanuel Quezada, Jaewon Shin, Shida Zhang, Asif Islam Khan, Shimeng Yu, Saibal Mukhopadhyay, Suman Datta
2025 J jnl
Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories.
CoRR
Ming-Yen Lee, Faaiq Waqar, Hanchen Yang, Muhammed Ahosan Ul Karim, Harsono Simka, Shimeng Yu
2025 J jnl
Backside Active Power Delivery With Hybrid DC-DC Converter Enabled by Amorphous Oxide Semiconductor Transistors.
IEEE Trans. Very Large Scale Integr. Syst.
Jungyoun Kwak, Sunbin Deng, Junmo Lee, Suman Datta, Shimeng Yu
2025 — conf
CMOS+X: Stacking Memories based on Oxide Transistors upon GPGPU Platforms.
MEMSYS
Faaiq Waqar, Ming-Yen Lee, Seongwon Yoon, Seongkwang Lim, Shimeng Yu
2025 J jnl
CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms.
CoRR
Faaiq Waqar, Ming-Yen Lee, Seongwon Yoon, Seongkwang Lim, Shimeng Yu
2025 J jnl
Capacitive Synaptor with Gate Surrounding Semiconductor Pillar Structure and Overturned Charge Injection for Compute-in-Memory.
Adv. Intell. Syst.
Choong-Ki Kim, James Read, Minji Shon, Tae-Hyeon Kim, Myung-Su Kim, Ji-Man Yu, Min-Soo Yoo, Yang-Kyu Choi, Shimeng Yu
2025 — conf
Comparative Study of Channel Materials for Ferroelectric NAND Applications.
IMW
Lance Fernandes, Prasanna Venkatesan Ravindran, Mengkun Tian, Yu-Hsin Kuo, Nashrah Afroze, Salma Soliman, Sanghyun Kang, Dyutimoy Chakraborty, Taeyoung Song, Chengyang Zhang, Kijoon Kim, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Asif Khan
2025 J jnl
Cryogenic Characterization of Ferroelectric Non-volatile Capacitors.
CoRR
Vadlamani Madhav, Dyutimoy Chakraborty, Jianwei Jia, Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Suman Datta, Shimeng Yu
2025 C conf
Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems.
ISCAS
Yuyao Kong, Jianwei Jia, Anni Lu, Faaiq G. Waqar, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu
2025 — conf
Enhanced Memory Performance in Ferroelectric NAND Applications: The Role of Tunnel Dielectric Position for Robust 10-Year Retention.
IRPS
Prasanna Venkatesan Ravindran, Andrea Padovani, Lance Fernandes, Priyankka Gundlapudi Ravikumar, Chinsung Park, Huy Tran, Zekai Wang, Hari Jayasankar, Amrit Garlapati, Taeyoung Song, Hang Chen, Winston Chern, Zheng Wang, Kijoon Kim, Jongho Woog, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Luca Larcher, Gaurav Thareja, Asif Khan
2025 A conf
FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash.
ICCAD
Sumukh Pinge, Ashkan Moradifirouzabadi, Keming Fan, Prasanna Venkatesan Ravindran, Tanvir H. Pantha, Po-Kai Hsu, Zheyu Li, Weihong Xu, Zihan Xia, Flavio Ponzina, Winston Chern, Taeyoung Song, Priyankka Gundlapudi Ravikumar, Mengkun Tian, Lance Fernandes, Huy Tran, Hari Jayasankar, Hang Chen, Chinsung Park, Amrit Garlapati, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Duygu Kuzum, Shimeng Yu, Sourav Dutta, Asif Khan, Tajana Rosing, Mingu Kang
2025 J jnl
FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash.
CoRR
Sumukh Pinge, Ashkan Moradifirouzabadi, Keming Fan, Prasanna Venkatesan Ravindran, Tanvir H. Pantha, Po-Kai Hsu, Zheyu Li, Weihong Xu, Zihan Xia, Flavio Ponzina, Winston Chern, Taeyoung Song, Priyankka Gundlapudi Ravikumar, Mengkun Tian, Lance Fernandes, Huy Tran, Hari Jayasankar, Hang Chen, Chinsung Park, Amrit Garlapati, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Duygu Kuzum, Shimeng Yu, Sourav Dutta, Asif Islam Khan, Tajana Rosing, Mingu Kang
2025 — conf
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference.
ASP-DAC
Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq G. Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu
2025 J jnl
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems.
CoRR
Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq G. Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu
2025 — conf
Machine Learning-Assisted Modeling of AC Stress-Induced Bias Temperature Instability in Oxide Channel Transistors for 2T Gain Cell eDRAM.
IRPS
Jungyoun Kwak, Chengyang Zhang, Gyujun Jeong, Omkar Phadke, Sharadindu Gopal Kirtania, Junmo Lee, Suman Datta, Shimeng Yu
2025 — conf
Modeling Dynamic Interplay Between Charge Traps and Polarization for Memory Window Enhancement in Gate Injection Layers.
IRPS
Minji Shon, Chinsung Park, Prasanna Venkatesan Ravindran, Lance Fernandes, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Suman Datta, Asif Khan, Shimeng Yu
2025 A* conf
Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration Memories.
DAC
Faaiq Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu
2025 J jnl
Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories.
CoRR
Faaiq G. Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu
2025 — conf
Monolithic 3D Stackable DRAM Design with BEOL-Compatible Oxide Channel Access Transistor.
IMW
Po-Kai Hsu, Sungwon Cho, Janak Sharda, Hyeonwoo Park, Suman Datta, Shimeng Yu
2025 — conf
NeuroSim Agent: Automated Compute-In-Memory Accelerator Deployment with Transferable Reinforcement Learning and Dynamic Design Space Pruning.
MLCAD
Ming-Yen Lee, Shimeng Yu
2025 J jnl
NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities.
CoRR
James Read, Ming-Yen Lee, Wei-Hsing Huang, Yuan-Chun Luo, Anni Lu, Shimeng Yu
2025 J jnl
Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache.
CoRR
Faaiq G. Waqar, Jungyoun Kwak, Junmo Lee, Minji Shon, MohammadHosein Gholamrezaei, Kevin Skadron, Shimeng Yu
2025 — conf
Radiation-Resilient Amorphous Indium Oxide FEFETs for Embedded Nonvolatile Memory.
IRPS
Sharadindu Gopal Kirtania, Faaiq G. Waqar, Dyutimoy Chakraborty, Jaewon Shin, Eknath Sarkar, Justin Reiss, Jason Dean Yeager, Douglas E. Wolfe, Shimeng Yu, Suman Datta
2025 A conf
Runtime Security Analysis of Monolithic 3D Embedded DRAM with Oxide-Channel Transistor.
DATE
Eduardo Ortega, Jungyoun Kwak, Shimeng Yu, Krishnendu Chakrabarty
2025 J jnl
SLIM: A Heterogeneous Accelerator for Edge Inference of Sparse Large Language Model via Adaptive Thresholding.
CoRR
Weihong Xu, Haein Choi, Po-Kai Hsu, Shimeng Yu, Tajana Rosing
2025 A* conf
Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving.
MICRO
Yue Pan, Zihan Xia, Po-Kai Hsu, Lanxiang Hu, Hyungyo Kim, Janak Sharda, Minxuan Zhou, Nam Sung Kim, Shimeng Yu, Tajana Rosing, Mingu Kang
2025 J jnl
Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving.
CoRR
Yue Pan, Zihan Xia, Po-Kai Hsu, Lanxiang Hu, Hyungyo Kim, Janak Sharda, Minxuan Zhou, Nam Sung Kim, Shimeng Yu, Tajana Rosing, Mingu Kang
2025 J jnl
System-Technology Co-Optimization Methodology for LLM Accelerators With Advanced Packaging.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Janak Sharda, Shimeng Yu
2025 — conf
Understanding Correlation Between Memory Window Closure, Leakage and Read Delay Effects for FEFET Reliability Improvement: Role of IL and FE Traps.
IRPS
Priyankka Gundlapudi Ravikumar, Andrea Padovani, Prasanna Venkatesan Ravindran, Chinsung Park, Nashrah Afroze, Mengkun Tian, Suman Datta, Shimeng Yu, Luca Larcher, Gaurav Thareja, Asif Khan
2024 — conf
3D Digital Compute-in-Memory Benchmark with A5 CFET Technology.
APCCAS
Minji Shon, Junmo Lee, Shimeng Yu
2024 B conf
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators.
ASPDAC
Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu
2024 J jnl
A FeFET-Based ADC Offset Robust Compute-In-Memory Architecture for Streaming Keyword Spotting (KWS).
IEEE Trans. Emerg. Top. Comput.
Yandong Luo, Johan Vanderhaegen, Oleg Rybakov, Martin Kraemer, Niel Warren, Shimeng Yu
2024 J jnl
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Po-Kai Hsu, Vaidehi Garg, Anni Lu, Shimeng Yu
2024 — conf
A Reconfigurable Bandpass Filter with Ferroelectric Devices for Intracardiac Electrograms Monitoring.
MWSCAS
Jianwei Jia, Zhenge Jia, Omkar Phadke, Gihun Choe, Yiyu Shi, Shimeng Yu
2024 — conf
Accelerator Design using 3D Stacked Capacitorless DRAM for Large Language Models.
AICAS
Janak Sharda, Po-Kai Hsu, Shimeng Yu
2024 — conf
Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits.
VLSI Technology and Circuits
Suman Datta, Eknath Sarkar, Khandker Akif Aabrar, Shan Deng, Jaewon Shin, Arijit Raychowdhury, Shimeng Yu, Asif Khan
2024 — conf
Back-side Design Methodology for Power Delivery Network and Clock Routing.
VLSI Technology and Circuits
Pruek Vanna-Iampikul, Hang Yang, Jungyoun Kwak, Joyce X. Hu, Amaan Rahman, Nesara Eranna Bethur, Callie Hao, Shimeng Yu, Sung Kyu Lim
2024 — conf
Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators.
VLSI Technology and Circuits
Ankit Kaul, Madison Manley, James Read, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir
2024 — conf
Comprehensive Time Dependent Dielectric Breakdown (TDDB) Characterization of Ferroelectric Capacitors Under Bipolar Stress Conditions.
IRPS
Priyankka Gundlapudi Ravikumar, Prasanna Venkatesan Ravindran, Khandker Akif Aabrar, Taeyoung Song, Sharadindu Gopal Kirtania, Dipjyoti Das, Chinsung Park, Nashrah Afroze, Mengkun Tian, Shimeng Yu, Ahmad Ehtesham Islam, Suman Datta, Souvik Mahapatra, Asif Islam Khan
2024 — conf
Demonstration of On-Chip Switched-Capacitor DC-DC Converters using BEOL Compatible Oxide Power Transistors and Superlattice MIM Capacitors.
VLSI Technology and Circuits
Sunbin Deng, Jungyoun Kwak, Junmo Lee, Dyutimoy Chakraborty, Jaewon Shin, Omkar Phadke, Sharadindu Gopal Kirtania, Chengyang Zhang, Khandker Akif Aabrar, Shimeng Yu, Suman Datta
2024 — conf
Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation.
IMW
Dipjyoti Das, Lance Fernandes, Prasanna Venkatesan Ravindran, Taeyoung Song, Chinsung Park, Nashrah Afroze, Mengkun Tian, Hang Chen, Winston Chem, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Asif Islam Khan
2024 A* conf
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization.
DAC
Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu
2024 J jnl
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Chun Luo, Anni Lu, Yandong Luo, Sou-Chi Chang, Uygar Avci, Shimeng Yu
2024 — conf
Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read.
IMW
Tae-Hyeon Kim, Yuan-Chun Luo, Omkar Phadke, James Read, Shimeng Yu
2024 J jnl
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices.
ACM Trans. Design Autom. Electr. Syst.
Yandong Luo, Shimeng Yu
2024 J jnl
Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge Inference.
CoRR
Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq G. Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu
2024 J jnl
HyperGen: compact and efficient genome sketching using hyperdimensional vectors.
Bioinform.
Weihong Xu, Po-Kai Hsu, Niema Moshiri, Shimeng Yu, Tajana Rosing
2024 — conf
Impact of In-Pixel Processing Circuit Non-idealities on Multi-object Tracking Accuracy for Autonomous Driving.
MWSCAS
Janak Sharda, Qiucheng Wu, Shiyu Chang, Shimeng Yu
2024 C conf
Monolithic 3D Transposable 3T Embedded DRAM with Back-end-of-line Oxide Channel Transistor.
ISCAS
Jungyoun Kwak, Gihun Choe, Junmo Lee, Shimeng Yu
2024 J jnl
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs
Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris H. Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, Hai Helen Li
2024 J jnl
NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junmo Lee, Anni Lu, Wantong Li, Shimeng Yu
2024 — conf
Optimization of Backside of Silicon-Compatible High Voltage Superlattice Capacitor for 12V-to-6V On-Chip Voltage Conversion.
DRC
Junmo Lee, Sunbin Deng, Jungyoun Kwak, Minji Shon, Suman Datta, Shimeng Yu
2024 — conf
P-type SnO Semiconductor Transistor and Application.
VLSI Technology and Circuits
C. C. Wang, C. C. Kuo, C. H. Wu, A. Lu, H. Y. Lee, C. F. Hsu, P. J. Tzeng, T. Y. Lee, F. R. Hou, M. H. Chang, S. C. Lai, K. Goto, Shimeng Yu, C. I. Wu, C. T. Lin, Y. M. Lin, X. Y. Bao
2024 J jnl
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.
CoRR
Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni
2024 — conf
Reliability Assesement of Ferroelectric nvCAP for Small-Signal Capacitive Read-Out.
IRPS
Omkar Phadke, Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Shimeng Yu
2024 J jnl
Semiconductor Memory Technologies: State-of-the-Art and Future Trends.
Computer
Shimeng Yu, Tae-Hyeon Kim
2024 J jnl
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads.
IEEE Trans. Very Large Scale Integr. Syst.
Yuan-Chun Luo, Anni Lu, Janak Sharda, Moritz Scherer, Jorge Tomás Gómez, Syed Shakib Sarwar, Ziyun Li, Reid Frederick Pinkham, Barbara De Salvo, Shimeng Yu
2024 J jnl
Towards Reverse-Engineering the Brain: Brain-Derived Neuromorphic Computing Approach with Photonic, Electronic, and Ionic Dynamicity in 3D integrated circuits.
CoRR
S. J. Ben Yoo, Luis El Srouji, Suman Datta, Shimeng Yu, Jean Anne C. Incorvia, Alberto Salleo, Volker J. Sorger, Juejun Hu, Lionel C. Kimerling, Kristofer Bouchard, Joy Geng, Rishidev Chaudhuri, Charan Ranganath, Randall C. O'Reilly
2023 — conf
A Reconfigurable Monolithic 3D Switched-Capacitor DC-DC Converter with Back-End-of-Line Oxide Channel Transistor.
MWSCAS
Jungyoun Kwak, Wantong Li, Shimeng Yu
2023 — conf
An In-Storage Processing Architecture with 3D NAND Heterogeneous Integration for Spectra Open Modification Search.
MEMSYS
Po-Kai Hsu, Weihong Xu, Tajana Rosing, Shimeng Yu
2023 B conf
CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception using Processing-in-Memory Accelerators.
IJCNN
Minah Lee, Anni Lu, Mandovi Mukherjee, Shimeng Yu, Saibal Mukhopadhyay
2023 — conf
Cold-FeFET as Embedded Non-Volatile Memory with Unlimited Cycling Endurance.
VLSI Technology and Circuits
Sharadindu Gopal Kirtania, Khandker Akif Aabrar, Asif Islam Khan, Shimeng Yu, Samyak Datta
2023 — conf
Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND Flash.
IMW
Sola Woo, Gihun Choe, Asif Islam Khan, Suman Datta, Shimeng Yu
2023 J jnl
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu
2023 C conf
Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices.
ISCAS
James Read, Wantong Li, Shimeng Yu
2023 — conf
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator.
BioCAS
Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu
2023 J jnl
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.
IEEE Trans. Very Large Scale Integr. Syst.
Wantong Li, Madison Manley, James Read, Ankit Kaul, Muhannad S. Bakir, Shimeng Yu
2023 J jnl
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators.
ACM Trans. Design Autom. Electr. Syst.
Shanshi Huang, Hongwu Jiang, Shimeng Yu
2023 — conf
Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors.
IRPS
Omkar Phadke, Khandker Akif Aabrar, Yuan-Chun Luo, Sharadindu Gopal Kirtania, Asif Islam Khan, Suman Datta, Shimeng Yu
2023 — conf
Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array.
AICAS
Wantong Li, Junmo Lee, Shimeng Yu
2023 A conf
PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration.
DATE
Wangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo
2023 J jnl
Proxima: Near-storage Acceleration for Graph-based Approximate Nearest Neighbor Search in 3D NAND.
CoRR
Weihong Xu, Junwei Chen, Po-Kai Hsu, Jaeyoung Kang, Minxuan Zhou, Sumukh Pinge, Shimeng Yu, Tajana Rosing
2023 A conf
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers.
DATE
Wantong Li, Yandong Luo, Shimeng Yu
2023 J jnl
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Anni Lu, Jae Hur, Yuan-Chun Luo, Hai Li, Dmitri E. Nikonov, Ian A. Young, Yang-Kyu Choi, Shimeng Yu
2023 J jnl
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute.
IEEE Trans. Circuits Syst. I Regul. Pap.
Janak Sharda, Wantong Li, Qiucheng Wu, Shiyu Chang, Shimeng Yu
2022 J jnl
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References.
IEEE J. Solid State Circuits
Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu
2022 — conf
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.
VLSI Technology and Circuits
Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu
2022 — conf
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.
ESSCIRC
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
2022 J jnl
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Yandong Luo, Sourav Dutta, Ankit Kaul, Sung Kyu Lim, Muhannad S. Bakir, Suman Datta, Shimeng Yu
2022 J jnl
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators.
IEEE Trans. Computers
Yandong Luo, Yuan-Chun Luo, Shimeng Yu
2022 — conf
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators.
ISVLSI
James Read, Wantong Li, Shimeng Yu
2022 — conf
A Thousand State Superlattice(SL) FEFET Analog Weight Cell.
VLSI Technology and Circuits
Khandker Akif Aabrar, Sharadindu Gopal Kirtania, A. Lu, A. Khanna, Wriddhi Chakraborty, M. San Jose, Shimeng Yu, Suman Datta
2022 — conf
A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor.
NANOARCH
Jungyoun Kwak, Gihun Choe, Shimeng Yu
2022 J jnl
A wearable sensor vest for social humanoid robots with GPGPU, IoT, and modular software architecture.
CoRR
Mohsen Jafarzadeh, Stephen Brooks, Shimeng Yu, Balakrishnan Prabhakaran, Yonas Tadesse
2022 J jnl
Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse.
ACM J. Emerg. Technol. Comput. Syst.
Yandong Luo, Panni Wang, Shimeng Yu
2022 J jnl
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices.
ACM Trans. Design Autom. Electr. Syst.
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
2022 J jnl
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators.
IEEE Des. Test
Hongwu Jiang, Wantong Li, Shanshi Huang, Stefan Cosemans, Francky Catthoor, Shimeng Yu
2022 — conf
BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators.
VLSI Technology and Circuits
Abhishek Khanna, Huacheng Ye, Y. Luo, G. Bajpai, M. San Jose, Wriddhi Chakraborty, Shimeng Yu, Patrick Fay, Suman Datta
2022 J jnl
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2022 — conf
Design-Technology Co-optimization for Cryogenic Tensor Processing Unit.
APCCAS
Dong Suk Kang, Shimeng Yu
2022 — conf
Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide.
VLSI Technology and Circuits
Xiao Lyu, Pragya R. Shrestha, Mengwei Si, Panni Wang, Junkang Li, Kin P. Cheung, Shimeng Yu, Peide D. Ye
2022 J jnl
GP3D: 3D NAND Based In-Memory Graph Processing Accelerator.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wonbo Shim, Shimeng Yu
2022 J jnl
Guest Editorial Memristive Circuits and Systems for Edge-Computing Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Georgios Ch. Sirakoulis, Alon Ascoli, Ronald Tetzlaff, Shimeng Yu
2022 — conf
Improved Endurance with Electron-Only Switching in Ferroelectric Devices.
DRC
Zheng Wang, Nujhat Tasneem, Hang Chen, Shimeng Yu, Winston Chern, Asif Islam Khan
2022 — conf
In-Memory 3D NAND Flash Hyperdimensional Computing Engine for Energy-Efficient SARS-CoV-2 Genome Sequencing.
IMW
Po-Kai Hsu, Shimeng Yu
2022 J jnl
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
2022 — conf
Machine Learning Assisted Statistical Variation Analysis of Ferroelectric Transistors: From Experimental Metrology to Predictive Modeling.
VLSI Technology and Circuits
Gihun Choe, Prasanna Venkatesan Ravindran, Anni Lu, Jae Hur, Maximilian Lederer, André Reck, Sarah Lombardo, Nashrah Afroze, Josh Kacher, Asif Islam Khan, Shimeng Yu
2022 J jnl
Nonvolatile Capacitive Crossbar Array for In-Memory Computing.
Adv. Intell. Syst.
Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu
2022 — conf
Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators.
IMW
Yandong Luo, Piyush Kumar, Yu-Ching Liao, William Hwang, Fen Xue, Wilman Tsai, Shan X. Wang, Azad Naeemi, Shimeng Yu
2022 J jnl
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saurabh Dash, Yandong Luo, Anni Lu, Shimeng Yu, Saibal Mukhopadhyay
2022 — conf
Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference.
IRPS
Jian Meng, Injune Yeo, Wonbo Shim, Li Yang, Deliang Fan, Shimeng Yu, Jae-sun Seo
2022 J jnl
Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference.
IEEE Micro
Jian Meng, Wonbo Shim, Li Yang, Injune Yeo, Deliang Fan, Shimeng Yu, Jae-sun Seo
2022 — conf
Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving.
AICAS
Wantong Li, Qiucheng Wu, Janak Sharda, Shiyu Chang, Shimeng Yu
2022 J jnl
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang
2021 — conf
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
ESSCIRC
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
2021 — conf
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
ESSDERC
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
2021 A conf
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training.
DATE
Yandong Luo, Yuan-Chun Luo, Shimeng Yu
2021 J jnl
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source.
IEEE J. Solid State Circuits
Bohan Lin, Yachuan Pang, Bin Gao, Jianshi Tang, Dong Wu, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, Meng-Fan Chang, He Qian, Huaqiang Wu
2021 A conf
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator.
DATE
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
2021 J jnl
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference.
ACM Trans. Design Autom. Electr. Syst.
Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu
2021 — conf
A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure.
IMW
Jae Hur, Yuan-Chun Luo, Zheng Wang, Wonbo Shim, Asif Islam Khan, Shimeng Yu
2021 J jnl
A wearable sensor vest for social humanoid robots with GPGPU, IoT, and modular software architecture.
Robotics Auton. Syst.
Mohsen Jafarzadeh, Stephen Brooks, Shimeng Yu, Balakrishnan Prabhakaran, Yonas Tadesse
2021 J jnl
AILC: Accelerate On-Chip Incremental Learning With Compute-in-Memory Technology.
IEEE Trans. Computers
Yandong Luo, Shimeng Yu
2021 — conf
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing.
IRPS
Wangxin He, Wonbo Shim, Shihui Yin, Xiaoyu Sun, Deliang Fan, Shimeng Yu, Jae-sun Seo
2021 — conf
Compute-in-Memory: From Device Innovation to 3D System Integration.
ESSDERC
Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-Chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng
2021 — conf
Compute-in-RRAM with Limited On-chip Resources.
AICAS
Anni Lu, Xiaochen Peng, Shimeng Yu
2021 C conf
Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator.
ISCAS
Panni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu
2021 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
2021 — conf
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing.
IMW
Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2021 — conf
Experimental RF Characterization of Ferroelectric Hafnium Zirconium Oxide Material at GHz for Microwave Applications.
DRC
Boce Lin, Gihun Choe, Jae Hur, Asif Islam Khan, Shimeng Yu, Hua Wang
2021 C conf
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning.
ISCAS
Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu
2021 J jnl
Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Beomseok Kang, Anni Lu, Yun Long, Daehyun Kim, Shimeng Yu, Saibal Mukhopadhyay
2021 J jnl
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst.
Gauthaman Murali, Xiaoyu Sun, Shimeng Yu, Sung Kyu Lim
2021 — conf
Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine.
IRPS
Wonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu
2021 — conf
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune.
NVMSA
Shanshi Huang, Hongwu Jiang, Shimeng Yu
2021 J jnl
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune.
CoRR
Shanshi Huang, Hongwu Jiang, Shimeng Yu
2021 J jnl
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell.
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 — conf
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro.
AICAS
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 J jnl
RRAM for Compute-in-Memory: From Inference to Training.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shimeng Yu, Wonbo Shim, Xiaochen Peng, Yandong Luo
2021 J jnl
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst.
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
2021 — conf
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security.
CICC
Wantong Li, Shanshi Huang, Xiaoyu Sun, Hongwu Jiang, Shimeng Yu
2021 J jnl
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Jian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-sun Seo
2021 — conf
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.
3DIC
Ankit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir
2020 — conf
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
ISSCC
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang
2020 — conf
8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator.
MWSCAS
Hongwu Jiang, Rui Liu, Shimeng Yu
2020 J jnl
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits
Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun
2020 A* conf
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.
DAC
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu
2020 C conf
A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out.
ISCAS
Yandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-sun Seo, Shimeng Yu
2020 J jnl
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses.
IEEE Trans. Computers
Yandong Luo, Shimeng Yu
2020 — conf
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine.
MEMSYS
Wonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu
2020 — conf
Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training.
ASP-DAC
Yandong Luo, Shimeng Yu
2020 J jnl
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint.
IEEE Trans. Very Large Scale Integr. Syst.
Anni Lu, Xiaochen Peng, Yandong Luo, Shimeng Yu
2020 J jnl
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays.
IEEE Trans. Computers
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
2020 — conf
Compute-in-Memory for AI: From Inference to Training.
VLSI-DAT
Shimeng Yu
2020 — conf
Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects.
CICC
Shimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang
2020 J jnl
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training.
CoRR
Xiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu
2020 — conf
Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction.
IRPS
Wonbo Shim, Yandong Luo, Jae-sun Seo, Shimeng Yu
2020 C conf
MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture.
ISCAS
Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu
2020 — conf
Modeling Multi-states in Ferroelectric Tunnel Junction.
DRC
Yuan-Chun Luo, Jae Hur, Panni Wang, Asif Islam Khan, Shimeng Yu
2020 J jnl
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Xiaochen Peng, Rui Liu, Shimeng Yu
2020 A conf
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories.
DATE
Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu
2020 J jnl
SMART Paths for Latency Reduction in ReRAM Processing-In-Memory Architecture for CNN Inference.
CoRR
Sho Ko, Shimeng Yu
2020 J jnl
The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures.
IEEE Des. Test
Xiaoming Chen, Kai Ni, Michael T. Niemier, Dayane Reis, Xiaoyu Sun, Panni Wang, Suman Datta, Xiaobo Sharon Hu, Xunzhao Yin, Matthew Jerry, Shimeng Yu, Ann Franchesca Laguna
2020 A conf
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption.
ICCAD
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
2019 J jnl
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang
2019 — conf
A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10
ISSCC
Yachun Pang, Bin Gao, Dong Wu, Shengyu Yi, Qi Liu, Wei-Hao Chen, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, He Qian, Meng-Fan Chang, Huaqiang Wu
2019 — conf
A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
ISSCC
Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang
2019 — conf
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.
MEMSYS
Hongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu
2019 A* conf
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.
DAC
Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian
2019 C conf
Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays.
ISCAS
Jiyong Woo, Shimeng Yu
2019 — conf
Evaluation of Single Event Effects in SRAM and RRAM Based Neuromorphic Computing System for Inference.
IRPS
Zhilu Ye, Rui Liu, Hugh J. Barnaby, Shimeng Yu
2019 J jnl
Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization.
CoRR
Fuxi Cai, Suhas Kumar, Thomas Van Vaerenbergh, Rui Liu, Can Li, Shimeng Yu, Qiangfei Xia, J. Joshua Yang, Raymond G. Beausoleil, Wei Lu, John Paul Strachan
2019 J jnl
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS.
CoRR
Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo
2019 J jnl
Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Xiaoyu Sun, Shimeng Yu
2019 J jnl
Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System.
IEEE Trans. Very Large Scale Integr. Syst.
Jiyong Woo, Shimeng Yu
2019 — conf
Inference engine benchmarking across technological platforms from CMOS to RRAM.
MEMSYS
Xiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu
2019 — conf
Investigating Dynamic Minor Loop of Ferroelectric Capacitor.
NVMTS
Panni Wang, Zheng Wang, Nujhat Tasneem, Jar Hur, Asif Islam Khan, Shimeng Yu
2019 J jnl
MAX
IEEE J. Emerg. Sel. Topics Circuits Syst.
Manqing Mao, Xiaochen Peng, Rui Liu, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti
2019 — conf
MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm Optimizations.
ICONS
Yandong Luo, Xiaochen Peng, Shimeng Yu
2019 J jnl
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.
IEEE Micro
Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim
2019 C conf
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory Architecture.
ISCAS
Xiaochen Peng, Rui Liu, Shimeng Yu
2019 J jnl
Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures.
IEEE Des. Test
Pai-Yu Chen, Shimeng Yu
2019 J jnl
Three-Dimensional nand Flash for Vector-Matrix Multiplication.
IEEE Trans. Very Large Scale Integr. Syst.
Panni Wang, Feng Xu, Bo Wang, Bin Gao, Huaqiang Wu, He Qian, Shimeng Yu
2018 — conf
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
ISSCC
Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang
2018 — conf
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
SiPS
Shihui Yin, Xiaoyu Sun, Shimeng Yu, Jae-sun Seo, Chaitali Chakrabarti
2018 — conf
A Versatile ReRAM-based Accelerator for Convolutional Neural Networks.
SiPS
Manqing Mao, Xiaoyu Sun, Xiaochen Peng, Shimeng Yu, Chaitali Chakrabarti
2018 — conf
Benchmark of RRAM based Architectures for Dot-Product Computation.
APCCAS
Xiaochen Peng, Shimeng Yu
2018 C conf
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing.
ISCAS
Jiyong Woo, Xiaochen Peng, Shimeng Yu
2018 J jnl
Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst.
Manqing Mao, Shimeng Yu, Chaitali Chakrabarti
2018 — conf
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
ASP-DAC
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
2018 J jnl
Large-Scale Neuromorphic Spiking Array Processors: A quest to mimic the brain.
CoRR
Chetan Singh Thakur, Jamal Molin, Gert Cauwenberghs, Giacomo Indiveri, Kundan Kumar, Ning Qiao, Johannes Schemmel, Runchun Wang, Elisabetta Chicca, Jennifer Olson Hasler, Jae-sun Seo, Shimeng Yu, Yu Cao, André van Schaik, Ralph Etienne-Cummings
2018 J jnl
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2018 J jnl
Neuro-Inspired Computing With Emerging Nonvolatile Memorys.
Proc. IEEE
Shimeng Yu
2018 J jnl
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
2018 A* conf
Parallelizing SRAM arrays with customized bit-cell for binary neural networks.
DAC
Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu
2018 — conf
Reliability perspective of resistive synaptic devices on the neuromorphic system performance.
IRPS
Pai-Yu Chen, Shimeng Yu
2018 Misc conf
Special session on reliability and vulnerability of neuromorphic computing systems.
VTS
Shimeng Yu, Chenchen Liu, Wujie Wen, Yiran Chen
2018 J jnl
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
2018 A conf
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
DATE
Xiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu
2017 — conf
1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays.
ASICON
Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei
2017 J jnl
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst.
Manqing Mao, Pai-Yu Chen, Shimeng Yu, Chaitali Chakrabarti
2017 J jnl
A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei
2017 — conf
Analysis of RRAM Reliability Soft-Errors on the Performance of RRAM-Based Neuromorphic Systems.
ISVLSI
Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei
2017 — conf
Analyzing inference robustness of RRAM synaptic array in low-precision neural network.
ESSDERC
Rui Liu, Heng-Yuan Lee, Shimeng Yu
2017 C conf
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array.
ISCAS
Rui Liu, Pai-Yu Chen, Shimeng Yu
2017 J jnl
Energy-Efficient Adaptive Computing With Multifunctional Memory.
IEEE Trans. Circuits Syst. II Express Briefs
Wenchao Qian, Pai-Yu Chen, Robert Karam, Ligang Gao, Swarup Bhunia, Shimeng Yu
2017 — conf
Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module.
AsianHOST
Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu
2017 J jnl
Improving efficiency in sparse learning with the feedforward inhibitory motif.
Neurocomputing
Zihan Xu, Steven Skorheim, Ming Tu, Visar Berisha, Shimeng Yu, Jae-sun Seo, Maxim Bazhenov, Yu Cao
2017 J jnl
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoyu Sun, Rui Liu, Yi-Ju Chen, Hsiao-Yun Chiu, Wei-Hao Chen, Meng-Fan Chang, Shimeng Yu
2017 — conf
Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems.
ACM Great Lakes Symposium on VLSI
Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei
2016 — conf
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation.
HOST
Rui Liu, Huaqiang Wu, Yachun Pang, He Qian, Shimeng Yu
2016 A conf
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
ICCAD
Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu
2016 J jnl
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array.
IEEE Trans. Very Large Scale Integr. Syst.
Pai-Yu Chen, Zhiwei Li, Shimeng Yu
2016 J jnl
Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning.
IEEE Trans. Multi Scale Comput. Syst.
Pai-Yu Chen, Ligang Gao, Shimeng Yu
2016 C conf
Design of a reliable RRAM-based PUF for compact hardware security primitives.
ISCAS
Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2016 A conf
MNSIM: Simulation platform for memristor-based neuromorphic computing system.
DATE
Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2016 J jnl
Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2016 C conf
Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing.
ISCAS
Pai-Yu Chen, Shimeng Yu
2016 — book
Resistive Random Access Memory (RRAM)
Shimeng Yu
2016 — conf
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM.
ACM Great Lakes Symposium on VLSI
Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia
2016 J jnl
Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.
J. Comput. Sci. Technol.
Lixue Xia, Peng Gu, Boxun Li, Tianqi Tang, Xiling Yin, Wenqin Huangfu, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang
2015 J jnl
Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures.
CoRR
Sukru Burc Eryilmaz, Duygu Kuzum, Shimeng Yu, H.-S. Philip Wong
2015 — conf
Exploiting resistive cross-point array for compact design of physical unclonable function.
HOST
Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu
2015 J jnl
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.
ACM Trans. Design Autom. Electr. Syst.
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2015 A conf
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
ICCAD
Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2015 — conf
On-chip Sparse Learning with Resistive Cross-point Array Architecture.
ACM Great Lakes Symposium on VLSI
Shimeng Yu, Yu Cao
2015 C conf
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings.
ICCD
Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2015 A* conf
Overcoming the challenges of crossbar resistive memory architectures.
HPCA
Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
2015 J jnl
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2015 — conf
Programming strategies to improve energy efficiency and reliability of ReRAM memory systems.
SiPS
Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2015 — conf
RRAM based synaptic devices for neuromorphic visual systems.
DSP
Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu, H.-S. Philip Wong
2015 C conf
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.
ISCAS
Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu
2015 — conf
Technological exploration of RRAM crossbar array for matrix-vector multiplication.
ASP-DAC
Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang
2015 A conf
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
DATE
Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2014 A conf
Architecting 3D vertical resistive memory for next-generation storage systems.
ICCAD
Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014 C conf
Design considerations of synaptic device for neuromorphic computing.
ISCAS
Shimeng Yu, Duygu Kuzum, H.-S. Philip Wong
2014 C conf
Design guidelines for 3D RRAM cross-point architecture.
ISCAS
Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong
2014 — conf
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation.
NANOARCH
Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula
2014 — conf
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
ASP-DAC
Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie
2014 — conf
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
BioCAS
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2014 C conf
Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices.
ISCAS
Shimeng Yu
2014 C conf
Overview of resistive switching memory (RRAM) switching mechanism and device modeling.
ISCAS
Shimeng Yu
2014 — conf
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.
BICA
Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao
2014 — conf
Reliability-aware cross-point resistive memory design.
ACM Great Lakes Symposium on VLSI
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014 C conf
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture.
ISCAS
Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu
2012 J jnl
Metal-Oxide RRAM.
Proc. IEEE
H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai