Shiheng Yang

26 papers Journal 14Unranked 12
YearRankTypeTitle / Venue / Authors
2026 — conf
27.1 A 20GHz Frequency Synthesizer with Spur-Shaping Modulator Achieving 46.2fs Jitter and -76.5dBc Worst-Case Fractional Spur.
ISSCC
Zonglin Ye, Yuxuan Sun, Longxiang Hou, Yuhan Ding, Yixuan Wen, Hongyang Zhang, Xinlin Geng, Qian Xie, Shiheng Yang, Zheng Wang
2025 — conf
18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW.
ISSCC
Han Zhao, Xuanhao Zhang, Qijin Deng, Jialin Hu, Zhenbing Li, Shiheng Yang, Jiaxin Liu
2025 — conf
A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C.
ISSCC
Yueduo Liu, Zihao Zhu, Xinyu Yang, Rongxin Bao, Zehao Zhang, Hongshuai Zhang, Jiaxin Liu, Zheng Wang, Mingkang Zhang, Na Yan, Jun Yin, Pui-In Mak, Shiheng Yang
2025 J jnl
A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xuanhao Zhang, Jialin Hu, Xingshuai Zou, Shiheng Yang, Jiaxin Liu
2025 J jnl
A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving -80.7dBc Fractional Spur.
IEEE Trans. Circuits Syst. II Express Briefs
Zonglin Ye, Hongyang Zhang, Yuxuan Sun, Xinlin Geng, Qian Xie, Shiheng Yang, Zheng Wang
2025 J jnl
Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jingrun Song, Xinyu Yang, Jiaxu Liu, Yueduo Liu, Zihao Zhu, Zhengxuan Han, Zehao Zhang, Jiaxin Liu, Hongshuai Zhang, Jun Yin, Pui-In Mak, Shiheng Yang
2025 J jnl
Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction.
IEEE Trans. Circuits Syst. II Express Briefs
Tailong Xu, Haoran Li, Xi Meng, Xiangxun Zhan, Yatao Peng, Jun Yin, Shiheng Yang, Chao Fan, Zhixiang Huang, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yueduo Liu, Zihao Zhu, Rongxin Bao, Jiahui Lin, Jun Yin, Qiang Li, Pui-In Mak, Shiheng Yang
2024 — conf
A Noise Shaping SAR ADC with kT/C Noise Cancellation and Mismatch Error Shaping.
ICTA
Tiange Yi, Zhenbing Li, Bing Du, Shiheng Yang, Jiaxin Liu
2023 J jnl
A 0.0043-mm
IEEE Trans. Very Large Scale Integr. Syst.
Yuchen Wei, Shiheng Yang, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Zehao Zhang, Yong Chen, Jun Yin, Pui-In Mak, Qiang Li
2023 J jnl
On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up.
IEEE Trans. Circuits Syst. II Express Briefs
Zehao Zhang, Shiheng Yang, Yueduo Liu, Zihao Zhu, Jiahui Lin, Rongxin Bao, Tailong Xu, Zhizhan Yang, Mingkang Zhang, Jiaxin Liu, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li
2022 — conf
A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS.
ICTA
Mingkang Zhang, Zihao Zhu, Yueduo Liu, Zehao Zhang, Rongxin Bao, Jiahui Lin, Haovu Zhuang, Jiaxin Liu, Xiong Zhou, Shiheng Yang, Qiang Li
2022 J jnl
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yueduo Liu, Rongxin Bao, Zihao Zhu, Shiheng Yang, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li
2021 J jnl
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Shiheng Yang, Jun Yin, Tailong Xu, Taimo Yi, Pui-In Mak, Qiang Li, Rui Paulo Martins
2021 — conf
A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration.
A-SSCC
Yan Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li
2021 — conf
A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC.
APCCAS
Xiaodan Zhou, Zehao Li, Yujie Wang, Xiong Zhou, Shiheng Yang, Jiaxin Liu, Qiang Li
2021 — conf
A Low-Power RC Oscillator with Offset and Path Delay Cancellation.
ICTA
Yueduo Liu, Zihao Zhu, Rongxin Bao, Shiheng Yang, Jiaxin Liu, Xiong Zhou, Qiang Li
2021 J jnl
Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs.
IEEE Open J. Circuits Syst.
Bojun Hu, Sanfeng Zhang, Xiangxin Pan, Xiangyu Zhao, Zhaoming Ding, Xiong Zhou, Shiheng Yang, Qiang Li
2020 J jnl
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.
IEEE Access
Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins
2019 J jnl
A 0.0056-mm
IEEE J. Solid State Circuits
Shiheng Yang, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019 J jnl
A 0.12-mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Ka-Fai Un, Gengzhen Qi, Jun Yin, Shiheng Yang, Shupeng Yu, Chio-In Ieong, Pui-In Mak, Rui Paulo Martins
2019 J jnl
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS.
IEEE J. Solid State Circuits
Shiheng Yang, Jun Yin, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2019 — conf
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.
ISSCC
Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins
2018 — conf
A 0.0056mm
ISSCC
Shiheng Yang, Jun Yin, Pui-In Mak, Rui Paulo Martins
2018 — conf
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS.
ISSCC
Jun Yin, Shiheng Yang, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2014 — conf
A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level.
APCCAS
Shiheng Yang, Pui-In Mak, Rui Paulo Martins