Shih-Lien Lu - RankMe

93 papers A* 14A 14B 4C 4Journal 31Unranked 25

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	O2MD²: A New Post-Quantum Cryptosystem With One-to-Many Distributed Key Management Based on Prime Modulo Double Encapsulation. IEEE Access Ricardo Neftali Pontaza Rodas, Ying-Dar Lin, Shih-Lien Lu, Keh-Jeng Chang
2020	—	`conf`	CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays. A-SSCC Zexi Ji, Wanyeong Jung, Jongchan Woo, Khushal Sethi, Shih-Lien Lu, Anantha P. Chandrakasan
2019	—	`conf`	A High Performance, Low Energy, Compact Masked 128-Bit AES in 22nm CMOS Technology. VLSI-DAT Yuan-Hsi Chou, Shih-Lien Lu
2019	—	`conf`	A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering. VLSI-DAT Shih-Lien Lu, Cheng-En Lee, Peter Noel, Saman Adham, Ted Wong, Jonathan Chang
2019	J	`jnl`	Guest Editors' Introduction: Intelligent Resource-Constrained Sensor Nodes. IEEE Des. Test Shreyas Sen, Arijit Raychowdhury, Shih-Lien Lu
2018	—	`conf`	A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations. DRC Insik Yoon, Muya Chang, Kai Ni, Matthew Jerry, Samantak Gangopadhyay, Gus Henry Smith, Tomer Hamam, Vijayakrishan Narayanan, Justin Romberg, Shih-Lien Lu, Suman Datta, Arijit Raychowdhury
2018	—	`conf`	A foundry's view of hardware security. VLSI-DAT Shih-Lien Lu
2017	—	`conf`	23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu
2016	J	`jnl`	DRAM Refresh Mechanisms, Penalties, and Trade-Offs. IEEE Trans. Computers Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob
2016	C	`conf`	Runahead Cache Misses Using Bloom Filter. PDCAT Xi Tao, Qi Zeng, Jih-Kwon Peir, Shih-Lien Lu
2016	C	`conf`	Small cache lookaside table for fast DRAM cache access. IPCCC Xi Tao, Qi Zeng, Jih-Kwon Peir, Shih-Lien Lu
2015	—	`conf`	A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu
2015	—	`conf`	Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance. MEMSYS Paul Tschirhart, Jim Stevens, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob
2015	—	`conf`	Evaluation methods of computer memory system. VLSI-DAT Shih-Lien Lu
2015	A*	`conf`	Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions. ISCA Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob
2015	A*	`conf`	Improving DRAM latency with dynamic asymmetric subarray. MICRO Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang
2014	—	`conf`	Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching. ICS 25th Anniversary Jih-Kwon Peir, Shih-Chang Kevin Lai, Shih-Lien Lu, Jared Stark, Konrad Lai
2014	J	`jnl`	DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
2014	A	`conf`	Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy. SC Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
2014	—	`conf`	Remapping NUCA: Improving NUCA Cache's Power Efficiency. HPCC/CSS/ICESS Hui Wang, Chunrong Lai, Yicong Huang, Shih-Lien Lu, Rui Wang, Zhongzhi Luan, Depei Qian
2014	A*	`conf`	Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. HPCA Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian
2013	A	`conf`	Guided Region-Based GPU Scheduling: Utilizing Multi-thread Parallelism to Hide Memory Latency. IPDPS Jianmin Chen, Xi Tao, Zhen Yang, Jih-Kwon Peir, Xiaoyuan Li, Shih-Lien Lu
2013	B	`conf`	Guided multiple hashing: Achieving near perfect balance for fast routing lookup. ICNP Xi Tao, Yan Qiao, Jih-Kwon Peir, Shigang Chen, Zhuo Huang, Shih-Lien Lu
2013	J	`jnl`	Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point. CoRR Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun
2013	J	`jnl`	Reducing cache and TLB power by exploiting memory region and privilege level semantics. J. Syst. Archit. Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi R. Iyer, Tong Li, Seung Eun Lee
2013	A*	`conf`	Technology comparison for large last-level caches (L HPCA Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob
2012	A	`conf`	Design for test and reliability in ultimate CMOS. DATE Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep P. Kulkarni, Vivek De, Dimiter Avresky
2012	J	`jnl`	Direct Compare of Information Coded With Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
2012	A	`conf`	Reducing L1 caches power by exploiting software semantics. ISLPED Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi R. Iyer, Tong Li, Seung Eun Lee
2012	A	`conf`	Scaling the "Memory Wall": Designer track. ICCAD Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held
2011	J	`jnl`	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De
2011	J	`jnl`	Adaptive Cache Design to Enable Reliable Low-Voltage Operation. IEEE Trans. Computers Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu
2011	J	`jnl`	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
2011	J	`jnl`	Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2011	A	`conf`	Distributed hardware matcher framework for SoC survivability. DATE Ilya Wagner, Shih-Lien Lu
2011	A*	`conf`	Energy-efficient cache design using variable-strength error-correcting codes. ISCA Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu
2011	J	`jnl`	Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2011	—	`conf`	Integrating formal verification and high-level processor pipeline synthesis. SASP Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2011	J	`jnl`	Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De
2010	—	`conf`	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2010	A*	`conf`	Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam
2010	A	`conf`	Automatic pipelining from transactional datapath specifications. DATE Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2010	—	`conf`	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
2010	—	`conf`	PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep P. Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
2010	A*	`conf`	Reducing cache power with low-cost, multi-bit error-correcting codes. ISCA Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
2010	—	`conf`	Resilient design in scaled CMOS for energy efficiency. ASP-DAC James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2010	A	`conf`	Resilient microprocessor design for high performance & energy efficiency. ISLPED Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
2009	J	`jnl`	2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2009	A*	`conf`	Circuit techniques for dynamic variation tolerance. DAC Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar
2009	—	`conf`	Content Addressable Memory for Low-Power and High-Performance Applications. CSIE (3) Ataur R. Patwary, Bibiche M. Geuskens, Shih-Lien Lu
2009	J	`jnl`	Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2009	A*	`conf`	Improving cache lifetime reliability at ultra-low voltages. MICRO Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu
2009	—	`conf`	Low power adaptive pipeline based on instruction isolation. ISQED Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra S. Yavatkar, Shih-Lien Lu, Nader Bagherzadeh
2009	A	`conf`	Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik
2009	J	`jnl`	Trading Off Cache Capacity for Low-Voltage Operation. IEEE Micro Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu
2008	—	`conf`	2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi
2008	J	`jnl`	A Desktop Computer with a Reconfigurable Pentium®. ACM Trans. Reconfigurable Technol. Syst. Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow
2008	J	`jnl`	Active Cache Emulator. IEEE Trans. Very Large Scale Integr. Syst. Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu
2008	—	`ch.`	Carry Logic. Wiley Encyclopedia of Computer Science and Engineering Shih-Lien Lu, Ravichandran Ramachandran
2008	—	`conf`	Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De
2008	B	`conf`	Novel FPGA based Haar classifier face detection algorithm acceleration. FPL Changjian Gao, Shih-Lien Lu
2008	A*	`conf`	Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. ISCA Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu
2007	B	`conf`	An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. FPL Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
2007	A	`conf`	An FPGA-based Pentium in a complete desktop system. FPGA Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh
2007	—	`conf`	Fine-Grained Redundancy in Adders. ISQED Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy
2007	C	`conf`	Improving the reliability of on-chip data caches under process variations. ICCD Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu
2007	J	`jnl`	RAMP: Research Accelerator for Multiple Processors. IEEE Micro John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic
2006	J	`jnl`	Asymmetric Clustering using a Register Cache. J. Instr. Level Parallelism Roger Morrison, Ben Lee, Shih-Lien Lu
2006	A	`conf`	Design, implementation, and verification of active cache emulator (ACE). FPGA Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
2006	—	`conf`	Research accelerator for multiple processors. Hot Chips Symposium David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek
2005	—	`conf`	A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De
2005	A	`conf`	Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu
2005	—	`conf`	Improving branch prediction accuracy with parallel conservative correctors. Conf. Computing Frontiers Chunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Pei-Chun Chen
2004	—	`conf`	Efficient Victim Mechanism on Sector Cache Organization. Asia-Pacific Computer Systems Architecture Conference Chunrong Lai, Shih-Lien Lu
2004	J	`jnl`	Speeding Up Processing with Approximation Circuits. Computer Shih-Lien Lu
2003	J	`jnl`	A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar
2003	C	`conf`	Hardware-based Pointer Data Prefetcher. ICCD Shih-Chang Lai, Shih-Lien Lu
2003	B	`conf`	Implementation of HW$im - A Real-Time Configurable Cache Simulator. FPL Shih-Lien Lu, Konrad Lai
2002	A	`conf`	Bloom filtering cache misses for accurate data speculation and prefetching. ICS Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai
2002	A	`conf`	Ditto Processor. DSN Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir
2002	A*	`conf`	Dynamic addressing memory arrays with physical locality. MICRO Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai
2001	J	`jnl`	Coming challenges in microarchitecture and architecture. Proc. IEEE Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen
2000	A*	`conf`	Performance improvement with circuit-level speculation. MICRO Tong Liu, Shih-Lien Lu
1998	A*	`conf`	Non-Stalling CounterFlow Architecture. HPCA Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu
1997	A*	`conf`	Advances of the Counterflow Pipeline Microarchitecture. HPCA Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller
1996	J	`jnl`	Efficient arithmetic using self-timing. IEEE Trans. Very Large Scale Integr. Syst. Ravichandran Ramachandran, Shih-Lien Lu
1995	J	`jnl`	Design of a static MIMD data flow processor using micropipelines. IEEE Trans. Very Large Scale Integr. Syst. Chih-Ming Chang, Shih-Lien Lu
1995	J	`jnl`	Implementation of micropipelines in enable/disable CMOS differential logic. IEEE Trans. Very Large Scale Integr. Syst. Shih-Lien Lu
1991	J	`jnl`	Evaluation of two-summand adders implemented in ECDL CMOS differential logic. IEEE J. Solid State Circuits Shih-Lien Lu, Milos D. Ercegovac
1990	J	`jnl`	A novel CMOS implementation of double-edge-triggered flip-flops. IEEE J. Solid State Circuits Shih-Lien Lu, Milos D. Ercegovac
1988	J	`jnl`	A safe single-phase clocking scheme for CMOS circuits. IEEE J. Solid State Circuits Shih-Lien Lu
1988	J	`jnl`	Device and circuit simulation interface for an integrated VLSI design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu
1988	J	`jnl`	Implementation of iterative networks with CMOS differential logic. IEEE J. Solid State Circuits Shih-Lien Lu