Shih-Hsu Huang

120 papers A* 6A 8B 1C 8Misc 1Journal 36Unranked 60

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A High-Performance Hardware Design for Polynomial Multiplication in the CRYSTALS-Kyber Algorithm. COOL CHIPS Hsueh Chen, Hsiu-Wei Chen, Shih-Hsu Huang, Po-Yuan Chen
2025	J	`jnl`	Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei-Che Cheng, Shih-Hsu Huang, Jin-Fu Li
2025	C	`conf`	PAT-ViT: Token Pruning-based Adversarial Tuning for Robust Vision Transformers. ISCAS Yun-Hao Yang, Yuan-June Luo, Wan-Jung Chen, An-Yeu Andy Wu, Shih-Hsu Huang, Mladen Berekovic
2025	—	`conf`	Special Session: Effective Design, Modeling and Testing Techniques for Digital Computing-in Memories with MAC Function. DFT Jin-Fu Li, Chun-Lung Hsu, Yu-Guang Chen, Ting-Yi Wu, Wei-Hung Lin, Shih-Hsu Huang, Yung-Chi Chia, Yu-Chieh Chen
2024	—	`conf`	An Approximate Method for The Fault Tolerance of SRAM-Based Near-Memory Multiply-Accumulate Units. ISPACS Yung-Chieh Lin, Liang-Ying Su, Shih-Hsu Huang
2024	J	`jnl`	An Overview of Trustworthy AI: Advances in IP Protection, Privacy-Preserving Federated Learning, Security Verification, and GAI Safety Alignment. IEEE J. Emerg. Sel. Topics Circuits Syst. Yue Zheng, Chip-Hong Chang, Shih-Hsu Huang, Pin-Yu Chen, Stjepan Picek
2024	—	`conf`	Automatic Tool for Translating Sum-of-Product Expressions into Behavior-Level CIM Circuits. ICCE-Taiwan Ting-Hao Chen, Shih-Hsu Huang, Chuan-Han Cheng, Li-Der Jeng
2024	C	`conf`	Design Flow for Incorporating Camouflaged Logic Gates to Enhance Hardware Security While Considering Timing Closure. ISCAS Liang-Ying Su, Shih-Hsu Huang
2024	J	`jnl`	Guest Editorial: Toward Trustworthy AI: Advances in Circuits, Systems, and Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. Shih-Hsu Huang, Pin-Yu Chen, Stjepan Picek, Chip-Hong Chang
2024	—	`conf`	Secure Control Logic Design for Dual Key Logic Locking. APCCAS Yi-Chen Chen, Shih-Hsu Huang
2024	—	`conf`	Securing Finite State Machines through Obfuscation Modes and Diverse Flip-Flop Configurations. ICCE-Taiwan Ya-Cheng Yu, Shih-Hsu Huang
2024	—	`conf`	Special Session: Enhancing Reliability in Digital Computing-in-Memory Architectures Through Approximation and Fault Tolerance Methods. DFT Shih-Hsu Huang, Chih-Li Hsiao, Wei-Che Cheng
2023	—	`conf`	A Metal-Only ECO Algorithm for Improving Hardware Security with Gate Camouflaging. ICCE-Taiwan Liang-Ying Su, Shih-Hsu Huang
2023	—	`conf`	An Automatic Facial Analysis System for The Detection of Pediatric Obstructive Sleep Apnea. ICCE-Taiwan Chia-Jo Lin, Shih-Hsu Huang, Wan-Yi Hsueh, Wei-Chung Hsu, Chih-Wen Su
2023	—	`conf`	Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. ITC-Asia Meng-Shan Wu, Yen-Lin Chua, Jin-Fu Li, Yun-Ting Chuan, Shih-Hsu Huang
2023	—	`conf`	Fault-Tolerant Near-Memory MAC Design with Redundant Memories. ICCE-Taiwan Hsin-Chen Lu, Shih-Hsu Huang
2023	—	`conf`	Hardware Trojans of Computing-In-Memories: Issues and Methods. DFT Shih-Hsu Huang, Wei-Che Cheng, Jin-Fu Li
2022	—	`conf`	A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations. AICAS Hsu-Yu Kao, Shih-Hsu Huang
2022	—	`conf`	A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration. ICCE-TW Bo-Xi Lai, Shih-Hsu Huang, Hsu-Yu Kao
2022	—	`conf`	Dataflow and Hardware Design for The Sharing of Feature Maps. ISOCC De-Yang Chiu, Shih-Hsu Huang
2022	—	`conf`	Design and Dataflow for Multibit SRAM-Based MAC Operations. ISOCC Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li
2022	—	`conf`	Network Pruning by Feature Map Sharing with K-Means Clustering. ICCE-TW De-Yang Chiu, Shih-Hsu Huang
2021	J	`jnl`	Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations. Sensors Yui-Kai Weng, Shih-Hsu Huang, Hsu-Yu Kao
2021	—	`conf`	Block-Based Compression for Reducing Indexing Cost of DNN Accelerators. ICCE-TW Yui-Kai Weng, Shih-Hsu Huang, Hsu-Yu Kao
2021	J	`jnl`	Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing. Sensors Hsu-Yu Kao, Xin-Jia Chen, Shih-Hsu Huang
2021	—	`conf`	ECO Timing Optimization with Data Paths and Clock Paths Considered. ISPACS Jia-Xiang Tang, Shih-Hsu Huang, Jui-Hung Hung
2021	—	`conf`	Hardware Implementation for Fending off Side-Channel Attacks. ICCE-TW Yi-Liang Hong, Yui-Kai Weng, Shih-Hsu Huang
2021	—	`conf`	Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators. ISOCC Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang
2021	C	`conf`	Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing. ICCE En-Hui Zhang, Shih-Hsu Huang
2020	J	`jnl`	A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process. IEEE Access Che-Wei Tung, Shih-Hsu Huang
2020	—	`conf`	A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design. ICCE-TW En-Hui Zhang, Shih-Hsu Huang
2020	Misc	`conf`	Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers. VTS Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng
2020	—	`conf`	Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design. ICCE-TW Shi-Rou Lin, Wei-Hung Lin, Shih-Hsu Huang, Chun-Lung Hsu, Chi-Tien Sun
2020	—	`conf`	Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function. ICCE-TW Yu-Hsuan Wu, Wei-Hung Lin, Shih-Hsu Huang
2020	—	`conf`	Low-Power Small-Area $3\times 3$ Convolution Hardware Design. ICCE-TW Xin-Jia Chen, Shih-Hsu Huang
2019	—	`conf`	3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. 3DIC Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li
2019	—	`conf`	A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 3DIC Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang
2019	—	`conf`	A Design Framework for Hardware Approximation of Deep Neural Networks. ISPACS Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang
2019	—	`conf`	Hardware Implementation for Multiple Activation Functions. ICCE-TW Chih-Hsiang Chang, Hsu-Yu Kao, Shih-Hsu Huang
2019	—	`conf`	IC Camouflaging by Using Universal Gates under Timing Constraints. ICCE-TW Po-Chieh Chang, Shih-Hsu Huang
2019	—	`conf`	Softsign Function Hardware Implementation Using Piecewise Linear Approximation. ISPACS Chih-Hsiang Chang, En-Hui Zhang, Shih-Hsu Huang
2018	—	`conf`	An Effective Approach for Building Low-Power General Activity-Driven Clock Trees. ISOCC Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng
2018	—	`conf`	Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. ISOCC Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang
2018	—	`conf`	Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization. NoCArc@MICRO Shih-Hsu Huang
2018	—	`conf`	TSV-aware 3D test wrapper chain optimization. VLSI-DAT Yu-Yi Wu, Shih-Hsu Huang
2017	—	`conf`	3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints. ATS Yen-Chun Ko, Shih-Hsu Huang
2017	A	`conf`	Overview of the 2017 CAD contest at ICCAD: Invited paper. ICCAD Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake
2017	J	`jnl`	Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang
2016	A	`conf`	Overview of the 2016 CAD contest at ICCAD. ICCAD Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake
2016	J	`jnl`	Power-mode-aware buffer synthesis for low-power clock skew minimization. IEICE Electron. Express Shih-Hsu Huang, Chun-Hua Cheng
2016	J	`jnl`	Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang
2016	C	`conf`	Top-level activity-driven clock tree synthesis with clock skew variation considered. ISCAS Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou
2015	J	`jnl`	Clock Period Minimization with Minimum Leakage Power. ACM Trans. Design Autom. Electr. Syst. Shih-Hsu Huang, Hua-Hsin Yeh, Yow-Tyng Nieh
2015	A	`conf`	Overview of the 2015 CAD Contest at ICCAD. ICCAD Natarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim
2014	—	`conf`	Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol. APCCAS Hua-Hsin Yeh, Wen-Pin Tu, Jian-Zhi Shen, Tung-Hua Yen, Shih-Hsu Huang
2014	A	`conf`	Leakage-power-aware clock period minimization. DATE Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh
2014	—	`conf`	Live demonstration: A low-power high-level synthesis system. APCCAS Hua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang
2014	—	`conf`	Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew. APCCAS Tsung-Tang Lin, Wen-Pin Tu, Shih-Hsu Huang
2014	J	`jnl`	Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shih-Hsu Huang, Hua-Hsin Yeh
2013	A	`conf`	Co-synthesis of data paths and clock control paths for minimum-period clock gating. DATE Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
2013	J	`jnl`	Low-power anti-aging zero skew clock gating. ACM Trans. Design Autom. Electr. Syst. Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan
2013	A	`conf`	Low-power timing closure methodology for ultra-low voltage designs. ICCAD Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
2012	C	`conf`	A formal approach to slack-driven high-level synthesis. ISCAS Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng
2012	—	`conf`	Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. ASP-DAC Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
2012	J	`jnl`	High-Level Synthesis for Minimum-Area Low-Power Clock Gating. J. Inf. Sci. Eng. Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li
2012	C	`conf`	NBTI-aware dual threshold voltage assignment for leakage power reduction. ISCAS Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi
2012	—	`conf`	Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. APCCAS Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang
2011	J	`jnl`	Accurate TSV Number Minimization in High-Level Synthesis. J. Inf. Sci. Eng. Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng
2011	J	`jnl`	Minimum Inserted Buffers for Clock Period Minimization. J. Inf. Sci. Eng. Shih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang
2011	—	`conf`	TSV sharing through multiplexing for TSV count minimization in high-level synthesis. SoCC Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang
2011	—	`conf`	Teaching three-dimensional system-in-package design automation in a semester course. MSE Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng
2010	—	`conf`	Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. ASP-DAC Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan
2010	J	`jnl`	Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. J. Inf. Sci. Eng. Shih-Hsu Huang, Chun-Hua Cheng
2009	J	`jnl`	An ILP approach to surge current minimization in high-level synthesis. IEICE Electron. Express Shih-Hsu Huang, Jheng-Fu Yeh, Chun-Hua Cheng
2009	J	`jnl`	Minimum-Period Register Binding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Hsu Huang, Chun-Hua Cheng
2009	J	`jnl`	Opposite-phase register switching for peak current minimization. ACM Trans. Design Autom. Electr. Syst. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2009	J	`jnl`	Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. J. Inf. Sci. Eng. Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng
2009	C	`conf`	Surge Current Minimization in High-level Synthesis. ISCAS Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang
2009	J	`jnl`	Synthesis of Anti-Aging Gated Clock Designs. J. Inf. Sci. Eng. Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan
2009	—	`conf`	Timing driven power gating in high-level synthesis. ASP-DAC Shih-Hsu Huang, Chun-Hua Cheng
2008	J	`jnl`	An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shih-Hsu Huang, Chun-Hua Cheng
2008	J	`jnl`	Module binding for low power clock gating. IEICE Electron. Express Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu
2008	J	`jnl`	Power-Management Scheduling for Peak Power Minimization. J. Inf. Sci. Eng. Shih-Hsu Huang, Chun-Hua Cheng
2008	A*	`conf`	Type-matching clock tree for zero skew clock gating. DAC Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu
2007	J	`jnl`	A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. J. Inf. Sci. Eng. Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2007	C	`conf`	A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. EUC Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang
2007	A*	`conf`	Clock Period Minimization with Minimum Delay Insertion. DAC Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh
2007	J	`jnl`	Clock skew scheduling with race conditions considered. ACM Trans. Design Autom. Electr. Syst. Shih-Hsu Huang, Yow-Tyng Nieh
2007	J	`jnl`	Operation scheduling for the synthesis of false loop free circuits. IEICE Electron. Express Shih-Hsu Huang, Chun-Hua Cheng
2007	J	`jnl`	Opposite-Phase Clock Tree for Peak Current Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
2007	—	`conf`	Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. EUC Workshops Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng
2006	—	`conf`	An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. JCIS Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
2006	J	`jnl`	An ILP Approach to the Slack Driven Scheduling Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shih-Hsu Huang, Chun-Hua Cheng
2006	—	`conf`	Fast multi-domain clock skew scheduling for peak current reduction. ASP-DAC Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2006	—	`conf`	High-Speed Fuzzy Inference Processor Using Active Rules Identification. JCIS Shih-Hsu Huang, Shi-Zhi Liu, Yi-Rung Chen, Jian-Yuan Lai
2006	—	`conf`	Operation Scheduling for False Loop Free Circuits. APCCAS Shih-Hsu Huang, Chun-Hua Cheng
2006	—	`conf`	Peak Power Minimization through Power Management Scheduling. APCCAS Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang
2006	A*	`conf`	Register binding for clock period minimization. DAC Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu
2006	A	`conf`	State re-encoding for peak current minimization. ICCAD Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2006	J	`jnl`	Synthesis of nonzero clock skew circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Hsu Huang, Yow-Tyng Nieh
2005	J	`jnl`	A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities. IEICE Trans. Inf. Syst. Shih-Hsu Huang, Jian-Yuan Lai
2005	—	`conf`	A formal approach to the slack driven scheduling problem in high-level synthesis. ISCAS (6) Shih-Hsu Huang, Chun-Hua Cheng
2005	—	`conf`	Floorplanning with clock tree estimation. ISCAS (6) Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh
2005	J	`jnl`	High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. J. Inf. Sci. Eng. Shih-Hsu Huang, Jian-Yuan Lai
2005	A*	`conf`	Minimizing peak current via opposite-phase clock tree. DAC Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu
2005	A*	`conf`	Race-condition-aware clock skew scheduling. DAC Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
2005	J	`jnl`	Three-dimension scheduling under multi-cycle interconnect communications. IEICE Electron. Express Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng
2005	—	`conf`	VLSI implementation of type-2 fuzzy inference processor. ISCAS (4) Shih-Hsu Huang, Yi-Rung Chen
2004	J	`jnl`	A Timing Driven Crosstalk Optimizer for Gridded Channel Routing. IEICE Trans. Inf. Syst. Shih-Hsu Huang, Yi-Siang Hsu, Chiu-Cheng Lin
2003	A	`conf`	Clock Period Minimization of Non-Zero Clock Skew Circuits. ICCAD Shih-Hsu Huang, Yow-Tyng Nieh
2002	—	`conf`	A timing driven approach for crosstalk minimization in gridded channel routing. APCCAS (1) Shih-Hsu Huang, Yi-Siang Hsu
2002	—	`conf`	An effective floorplan-based power distribution network design methodology under reliability constraints. ISCAS (1) Shih-Hsu Huang, Chu-Liao Wang
2002	—	`conf`	Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions. APCCAS (2) Shih-Hsu Huang, Wen-Hon Peng, Jian-Yuan Lai
2001	B	`conf`	A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture. FUZZ-IEEE Shih-Hsu Huang, Jian-Yuan Lai
2001	—	`conf`	An effective low power design methodology based on interconnect prediction. SLIP Shih-Hsu Huang
2000	—	`conf`	A Reliable Clock Tree Design Methodology for ASIC Designs. ISQED Mely Chen Chi, Shih-Hsu Huang
1995	J	`jnl`	A new approach to schedule operations across nested-ifs and nested-loops. Microprocess. Microprogramming Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
1995	J	`jnl`	A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. Microprocess. Microprogramming Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang
1995	—	`conf`	Synthesis of false loop free circuits. ASP-DAC Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang
1992	A*	`conf`	A new approach to schedule operations across nested-ifs and nested-loops. MICRO Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang