Shih-Chieh Chang

182 papers A* 17A 35B 3C 6Journal 65Unranked 56

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-in-Memory Macro for Hybrid SNN-CNN Edge Computing. ISSCC Yao-Kai Yeh, Jian-Wei Su, Ting-Hao Hsu, Mai Tseng, Jen-Chun Tien, Ko-Chi Chen, Chih-Yen Yue, Yu-En Lin, Yu-Jia Hu, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Hung-Hsi Hsu, De-Qi You, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2026	—	`conf`	Event Camera Deraining Using Transformer Networks with Time-Space Attention. VISAPP (2) Pin-Yuan Yang, Shih-Chieh Chang
2025	J	`jnl`	CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. CoRR Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang
2025	—	`conf`	CNN Model Optimization Using a Hybrid Approach of Genetic Algorithm-based Pruning and Retraining with Knowledge Distillation. ACM Great Lakes Symposium on VLSI Kuan-Ling Chou, Cheng-Lung Wang, Yung-Chih Chen, Wuqian Tang, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang
2025	—	`conf`	Coloring 3D Avatars with Single-Image. VISIGRAPP (2): VISAPP Pin-Yuan Yang, Yu-Shan Deng, Chieh-Shan Lin, An-Chun Luo, Shih-Chieh Chang
2025	A	`conf`	Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration. DATE Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Peng-Wen Chen, Po-Yu Chen, Hao-Yun Chen, Yung-Chih Chen, Chun-Yao Wang, Shih-Chieh Chang
2025	J	`jnl`	Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset. IEEE J. Emerg. Sel. Topics Circuits Syst. Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Ching-Iang Li, Yung-Sheng Chang, Ming-Ji Dai, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang
2025	A*	`conf`	Real-Time Dynamic IR-drop Prediction for IR ECO. DAC Yu-Che Lee, Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Jia-Wei Lin, Hsun-Wei Pao, Yung-Chih Chen, Yi-Ting Li, Wuqian Tang, Shih-Chieh Chang, Chun-Yao Wang
2024	J	`jnl`	8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	J	`jnl`	A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE J. Solid State Circuits Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	A	`conf`	A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang
2024	J	`jnl`	An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE J. Solid State Circuits Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	C	`conf`	CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. ISCAS Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang
2024	—	`conf`	Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. VLSI Technology and Circuits Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
2024	—	`conf`	IR drop Prediction Based on Machine Learning and Pattern Reduction. ACM Great Lakes Symposium on VLSI Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, Chun-Yao Wang
2024	—	`conf`	Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method. SOCC Wuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang
2024	—	`conf`	Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. VLSI Technology and Circuits Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang
2023	J	`jnl`	A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang
2023	—	`conf`	A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. ISSCC Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2023	J	`jnl`	A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2023	—	`conf`	Optimization of AI SoC with Compiler-assisted Virtual Design Platform. ISPD Chih-Tsun Huang, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung, Shih-Chieh Chang
2023	—	`conf`	U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. VLSI Technology and Circuits Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
2022	—	`conf`	A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. ISSCC Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang
2022	A	`conf`	Robust Binary Neural Network against Noisy Analog Computation. DATE Zong-Han Lee, Fu-Cheng Tsai, Shih-Chieh Chang
2021	—	`conf`	16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. ISSCC Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2021	—	`conf`	A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou
2021	J	`jnl`	Dynamic Workload Allocation for Edge Computing. IEEE Trans. Very Large Scale Integr. Syst. Yi-Wen Hung, Yung-Chih Chen, Chi Lo, Austin Go So, Shih-Chieh Chang
2020	—	`conf`	15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. ISSCC Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang
2020	A	`conf`	Accuracy Tolerant Neural Networks Under Aggressive Power Optimization. DATE Xiang-Xiu Wu, Yi-Wen Hung, Yung-Chih Chen, Shih-Chieh Chang
2020	—	`conf`	AirConcierge: Generating Task-Oriented Dialogue via Efficient Large-Scale Knowledge Retrieval. EMNLP (Findings) Chieh-Yang Chen, Pei-Hsin Wang, Shih-Chieh Chang, Da-Cheng Juan, Wei Wei, Jia-Yu Pan
2020	J	`jnl`	Calibrated BatchNorm: Improving Robustness Against Noisy Weights in Neural Networks. CoRR Li-Huang Tsai, Shih-Chieh Chang, Yu-Ting Chen, Jia-Yu Pan, Wei Wei, Da-Cheng Juan
2020	J	`jnl`	Contextual Temperature for Language Modeling. CoRR Pei-Hsin Wang, Sheng-Iou Hsieh, Shih-Chieh Chang, Yu-Ting Chen, Jia-Yu Pan, Wei Wei, Da-Chang Juan
2020	B	`conf`	Person Identification by Walking Gesture Using Skeleton Sequences. ACIVS Chu-Chien Wei, Li-Huang Tsai, Hsin-Ping Chou, Shih-Chieh Chang
2020	—	`conf`	Remix: Rebalanced Mixup. ECCV Workshops (6) Hsin-Ping Chou, Shih-Chieh Chang, Jia-Yu Pan, Wei Wei, Da-Cheng Juan
2020	J	`jnl`	Remix: Rebalanced Mixup. CoRR Hsin-Ping Chou, Shih-Chieh Chang, Jia-Yu Pan, Wei Wei, Da-Cheng Juan
2019	—	`conf`	Aging-aware chip health prediction adopting an innovative monitoring strategy. ASP-DAC Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang
2019	—	`conf`	Complement Objective Training. ICLR (Poster) Hao-Yun Chen, Pei-Hsin Wang, Chun-Hao Liu, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan
2019	J	`jnl`	Complement Objective Training. CoRR Hao-Yun Chen, Pei-Hsin Wang, Chun-Hao Liu, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan
2019	—	`conf`	Hierarchical LSTM: Modeling Temporal Dynamics and Taxonomy in Location-Based Mobile Check-Ins. PAKDD (2) Chun-Hao Liu, Da-Cheng Juan, Xuan-An Tseng, Wei Wei, Yu-Ting Chen, Jia-Yu Pan, Shih-Chieh Chang
2019	A*	`conf`	Improving Adversarial Robustness via Guided Complement Entropy. ICCV Hao-Yun Chen, Jhao-Hong Liang, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan
2019	J	`jnl`	Improving Adversarial Robustness via Guided Complement Entropy. CoRR Hao-Yun Chen, Jhao-Hong Liang, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan
2019	J	`jnl`	Learning with Hierarchical Complement Objective. CoRR Hao-Yun Chen, Li-Huang Tsai, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan
2018	J	`jnl`	An Adaptive Mechanism for Designing Efficient Snoop Filters. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Hung Lin, Sze-Chen Cho, Shih-Chieh Chang
2018	J	`jnl`	Contactless Testing for Prebond Interposers. IEEE Trans. Very Large Scale Integr. Syst. Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee, Shih-Chieh Chang
2018	J	`jnl`	MONAS: Multi-Objective Neural Architecture Search using Reinforcement Learning. CoRR Chi-Hung Hsu, Shu-Huan Chang, Da-Cheng Juan, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Shih-Chieh Chang
2018	J	`jnl`	Searching Toward Pareto-Optimal Device-Aware Neural Architectures. CoRR An-Chieh Cheng, Jin-Dong Dong, Chi-Hung Hsu, Shu-Huan Chang, Min Sun, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan
2018	A	`conf`	Searching toward pareto-optimal device-aware neural architectures. ICCAD An-Chieh Cheng, Jin-Dong Dong, Chi-Hung Hsu, Shu-Huan Chang, Min Sun, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan
2018	J	`jnl`	Sensor-Based Time Speculation in the Presence of Timing Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang
2017	C	`conf`	A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing. ICCD Chi Lo, Yu-Yi Su, Chun-Yi Lee, Shih-Chieh Chang
2017	—	`conf`	CN-SIM: A cycle-accurate full system power delivery noise simulator. ASP-DAC Kassan Unda, Chung-Han Chou, Shih-Chieh Chang, Cheng Zhuo, Yiyu Shi
2017	—	`conf`	DC-Prophet: Predicting Catastrophic Machine Failures in DataCenters. ECML/PKDD (3) You-Luen Lee, Da-Cheng Juan, Xuan-An Tseng, Yu-Ting Chen, Shih-Chieh Chang
2017	J	`jnl`	DC-Prophet: Predicting Catastrophic Machine Failures in DataCenters. CoRR You-Luen Lee, Da-Cheng Juan, Xuan-An Tseng, Yu-Ting Chen, Shih-Chieh Chang
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	J	`jnl`	Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control. ACM Trans. Design Autom. Electr. Syst. Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
2017	—	`conf`	Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang
2017	J	`jnl`	Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units. IEEE Trans. Parallel Distributed Syst. Cheng-Hung Lin, Jin-Cheng Li, Chen-Hsiung Liu, Shih-Chieh Chang
2017	J	`jnl`	Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang
2016	—	`conf`	A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization. ASP-DAC Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang
2016	J	`jnl`	High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols. IEEE Trans. Very Large Scale Integr. Syst. Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
2016	—	`conf`	Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. SoCC Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang
2016	—	`conf`	RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan. AsianHOST Travis E. Schulze, Kevin A. Kwiat, Charles A. Kamhoua, Shih-Chieh Chang, Yiyu Shi
2016	J	`jnl`	Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang
2015	J	`jnl`	A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning. IEEE Trans. Very Large Scale Integr. Syst. Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang
2015	—	`conf`	Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments. ASP-DAC Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Jean Tsao, Shih-Chieh Chang
2015	J	`jnl`	Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Guang Chen, Wan-Yu Wen, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang
2015	—	`conf`	Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation. ISPD Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi, Shih-Chieh Chang
2015	J	`jnl`	Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability. IEEE Trans. Very Large Scale Integr. Syst. Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
2014	J	`jnl`	A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wan-Yu Wen, Jin-Cheng Li, Sheng-Yuan Lin, Jing-Yi Chen, Shih-Chieh Chang
2014	—	`conf`	Concurrency-oriented SoC re-certification by reusing block-level test vectors. ISQED Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Shih-Chieh Chang
2014	A*	`conf`	Contactless Stacked-die Testing for Pre-bond Interposers. DAC Jui-Hung Chien, Ruei-Siang Hsu, Hsueh-Ju Lin, Ka-Yi Yeh, Shih-Chieh Chang
2014	A*	`conf`	Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs. DAC Yu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wan-Yu Wen, Yiyu Shi, Shih-Chieh Chang
2014	J	`jnl`	Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Guang Chen, Hui Geng, Kuan-Yu Lai, Yiyu Shi, Shih-Chieh Chang
2014	A	`conf`	Package geometric aware thermal analysis by infrared-radiation thermal images. DATE Jui-Hung Chien, Hao Yu, Ruei-Siang Hsu, Hsueh-Ju Lin, Shih-Chieh Chang
2014	J	`jnl`	Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cody Hao Yu, Chiao-Ling Lung, Yi-Lun Ho, Ruei-Siang Hsu, Ding-Ming Kwai, Shih-Chieh Chang
2014	A	`conf`	Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits. DATE Yu-Guang Chen, Kuan-Yu Lai, Ming-Chao Lee, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang
2013	A*	`conf`	A novel fuzzy matching model for lithography hotspot detection. DAC Sheng-Yuan Lin, Jing-Yi Chen, Jin-Cheng Li, Wan-Yu Wen, Shih-Chieh Chang
2013	J	`jnl`	Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs. IEEE Trans. Computers Cheng-Hung Lin, Chen-Hsiung Liu, Lung-Sheng Chien, Shih-Chieh Chang
2013	J	`jnl`	Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans. Very Large Scale Integr. Syst. Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang
2013	A	`conf`	Low-power timing closure methodology for ultra-low voltage designs. ICCAD Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
2013	—	`conf`	On the futility of thermal through-silicon-vias. VLSI-DAT Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Yiyu Shi, Jui-Hung Chien, Shih-Chieh Chang
2013	J	`jnl`	Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. IEEE Access Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang
2013	J	`jnl`	Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chiao-Ling Lung, Yu-Shih Su, Hsih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang
2012	A	`conf`	A probabilistic analysis method for functional qualification under Mutation Analysis. DATE Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen
2012	J	`jnl`	Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ming-Chao Lee, Yiyu Shi, Shih-Chieh Chang
2012	A	`conf`	Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms. ICCAD Yu-Guang Chen, Yiyu Shi, Kuan-Yu Lai, Hui Geng, Shih-Chieh Chang
2012	—	`conf`	Efficient on-line module-level wake-up scheduling for high performance multi-module designs. ISPD Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu, Shih-Chieh Chang
2012	A*	`conf`	Memory-efficient pattern matching architectures using perfect hashing on graphic processing units. INFOCOM Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang, Wing-Kai Hon
2012	A	`conf`	Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms. DATE Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang
2012	—	`conf`	Post silicon skew tuning: Survey and analysis. ASP-DAC Mac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang
2012	J	`jnl`	Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic. ACM Trans. Design Autom. Electr. Syst. Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang
2011	A	`conf`	A robust architecture for post-silicon skew tuning. ICCAD Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang
2011	B	`conf`	Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU. GLOBECOM Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang
2011	A	`conf`	Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. ISLPED Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang
2011	J	`jnl`	Efficient Pattern Matching Algorithm for Memory Architecture. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Hung Lin, Shih-Chieh Chang
2011	A*	`conf`	Fault-tolerant 3D clock network. DAC Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang
2011	—	`conf`	NBTI-aware power gating design. ASP-DAC Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, Shih-Chieh Chang
2011	A	`conf`	On the preconditioner of conjugate gradient method - A power grid simulation perspective. ICCAD Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang
2011	J	`jnl`	Performance Optimization Using Variable-Latency Design Style. IEEE Trans. Very Large Scale Integr. Syst. Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2011	—	`conf`	TSV fault-tolerant mechanisms with application to 3D clock networks. ISOCC Chiao-Ling Lung, Jui-Hung Chien, Yiyu Shi, Shih-Chieh Chang
2011	A	`conf`	Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. DATE Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang
2011	A	`conf`	Useful-skew clock optimization for multi-power mode designs. ICCAD Hsuan-Ming Chou, Hao Yu, Shih-Chieh Chang
2010	B	`conf`	Accelerating String Matching Using Multi-Threaded Algorithm on GPU. GLOBECOM Cheng-Hung Lin, Sheng-Yu Tsai, Chen-Hsiung Liu, Shih-Chieh Chang, Jyuo-Min Shyu
2010	J	`jnl`	An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs. IEEE Trans. Very Large Scale Integr. Syst. Da-Cheng Juan, Yu-Ting Chen, Ming-Chao Lee, Shih-Chieh Chang
2010	A*	`conf`	An efficient phase detector connection structure for the skew synchronization system. DAC Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang
2010	J	`jnl`	Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang
2010	A	`conf`	Clock skew optimization considering complicated power modes. DATE Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang
2010	J	`jnl`	Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang
2010	A	`conf`	Synthesis of an efficient controlling structure for post-silicon clock skew minimization. ICCAD Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang
2009	A	`conf`	An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs. ICCAD Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Chieh Chang
2009	J	`jnl`	Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang
2009	J	`jnl`	Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing. IEEE Trans. Very Large Scale Integr. Syst. De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang
2009	J	`jnl`	Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2009	A	`conf`	Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ICCAD Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang
2008	A	`conf`	A novel sequential circuit optimization with clock gating logic. ICCAD Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang
2008	—	`conf`	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang
2008	J	`jnl`	Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang
2008	C	`conf`	Timing analysis considering IR drop waveforms in power gating designs. ICCD Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007	A*	`conf`	An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007	A	`conf`	An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. ICCAD Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang
2007	A	`conf`	Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang
2007	—	`conf`	Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis. ISQED Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang
2007	A	`conf`	Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007	A	`conf`	Engineering change using spare cells with constant insertion. ICCAD Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007	A*	`conf`	Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. DAC De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang
2007	—	`conf`	Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. ISQED Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho
2007	J	`jnl`	Optimization of Pattern Matching Circuits for Regular Expression on FPGA. IEEE Trans. Very Large Scale Integr. Syst. Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
2007	—	`conf`	Optimization of pattern matching algorithm for memory based architecture. ANCS Cheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang
2006	—	`conf`	Delay variation tolerance for domino circuits. ASP-DAC Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang
2006	A	`conf`	Efficient Boolean characteristic function for fast timed ATPG. ICCAD Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang
2006	—	`conf`	Language-Based High Level Transaction Extraction on On-chip Buses. ISQED Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen
2006	J	`jnl`	Multiple wire reconnections based on implication flow graph. ACM Trans. Design Autom. Electr. Syst. Zhong-Zhen Wu, Shih-Chieh Chang
2006	—	`conf`	Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang
2006	J	`jnl`	Power minimization for dynamic PLAs. IEEE Trans. Very Large Scale Integr. Syst. Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
2006	A*	`conf`	Timing driven power gating. DAC De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh
2006	J	`jnl`	Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. C.-T. Hsieh, J.-C. Lin, Shih-Chieh Chang
2005	—	`conf`	Design and design automation of rectification logic for engineering change. ASP-DAC Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone
2005	—	`conf`	FPGA technology mapping optimization by rewiring algorithms. ISCAS (6) Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang
2005	—	`conf`	Power estimation starategies for a low-power security processor. ASP-DAC Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang
2005	—	`conf`	Power minimization for dynamic PLAs. ASP-DAC Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh
2004	A	`conf`	A vectorless estimation of maximum instantaneous current for sequential circuits. ICCAD Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang
2004	A*	`conf`	Re-synthesis for delay variation tolerance. DAC Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu
2004	—	`conf`	Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. Asian Test Symposium Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang
2003	J	`jnl`	Embedded core test generation using broadcast test architecture and netlist scrambling. IEEE Trans. Reliab. J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh
2002	—	`conf`	A don't-care based image circuit for function verification. ISCAS (5) Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang
2002	A	`conf`	Crosstalk Alleviation for Dynamic PLAs. DATE Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
2002	J	`jnl`	Crosstalk alleviation for dynamic PLAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai
2002	J	`jnl`	Novel Techniques for Improving Testability Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang
2001	J	`jnl`	A timing-driven pseudoexhaustive testing for VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Jiann-Chyi Rau
2001	J	`jnl`	Charge-sharing alleviation and detection for CMOS domino circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
2001	J	`jnl`	Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. VLSI Design Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das
2001	—	`conf`	Embedded Core Testing Using Broadcast Test Architecture. DFT J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone
2001	J	`jnl`	Random Pattern Testability Enhancement by Circuit Rewiring. VLSI Design Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das
2001	J	`jnl`	Theorems and extensions of single wire replacement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Zhong-Zhen Wu
2000	C	`conf`	A compact factored form for a Boolean function. ISCAS Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang
2000	C	`conf`	A timing-driven pseudo-exhaustive testing of VLSI circuits. ISCAS Shih-Chieh Chang, Jiann-Chyi Rau
2000	—	`conf`	Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits. LATW Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000	—	`conf`	Charge sharing fault analysis and testing for CMOS domino logic circuits. Asian Test Symposium Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
2000	—	`conf`	Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. DFT Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000	—	`conf`	Novel techniques for improving testability analysis. Asian Test Symposium Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang
2000	A	`conf`	Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. ICCAD Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
2000	J	`jnl`	TAIR: testability analysis by implication reasoning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang
2000	A	`conf`	Wire Reconnections Based on Implication Flow Graph. ICCAD Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu
1999	—	`conf`	Charge Sharing Fault Detection for CMOS Domino Logic Circuits. DFT Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
1999	J	`jnl`	Circuit Optimization by Rewiring. IEEE Trans. Computers Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska
1999	J	`jnl`	Efficient Boolean division and substitution using redundancy addition and removing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, David Ihsin Cheng
1999	A*	`conf`	Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
1999	—	`conf`	Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
1999	A	`conf`	Synthesis for multiple input wires replacement of a gate for wiring consideration. ICCAD Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu
1998	A	`conf`	A novel combinational testability analysis by considering signal correlation. ITC Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai
1998	A	`conf`	A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. ITC Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu
1998	A*	`conf`	Efficient Boolean Division and Substitution. DAC Shih-Chieh Chang, David Ihsin Cheng
1997	J	`jnl`	Postlayout logic restructuring using alternative wires. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
1996	A	`conf`	Fast Boolean optimization by rewiring. ICCAD Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska
1996	—	`conf`	Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares. ED&TC Shih-Chieh Chang, Malgorzata Marek-Sadowska
1996	J	`jnl`	Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1996	J	`jnl`	Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang
1995	A*	`conf`	An Efficient Algorithm for Local Don't Care Sets Calculation. DAC Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1995	A*	`conf`	Logic Synthesis for Engineering Change. DAC Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1994	A*	`conf`	Layout Driven Logic Synthesis for FPGAs. DAC Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
1994	—	`conf`	Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska
1994	A	`conf`	Perturb and simplify: multi-level boolean network optimizer. ICCAD Shih-Chieh Chang, Malgorzata Marek-Sadowska
1992	C	`conf`	Technology Mapping via Transformations of Function Graphs. ICCD Shih-Chieh Chang, Malgorzata Marek-Sadowska