Shigeyoshi Watanabe

35 papers B 4C 1Journal 21Unranked 9
YearRankTypeTitle / Venue / Authors
2017 J jnl
The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer.
IEICE Trans. Inf. Syst.
Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman
2016 — conf
The performance evaluation of 3D torus using link-sharing method in NoC router.
ICCE-TW
Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman
2015 J jnl
An Adaptive Routing Algorithm of 2-D Torus Network Based on Turn Model: The Communication Performance.
Int. J. Netw. Comput.
Yasuyuki Miura, Kentaro Shimozono, Naohisa Fukase, Shigeyoshi Watanabe, Kazuya Matoyama
2014 J jnl
Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe
2014 J jnl
Reconfigurable Dynamic Logic Circuit Generating
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Manabu Kobayashi, Hiroshi Ninomiya, Yasuyuki Miura, Shigeyoshi Watanabe
2014 — conf
The Proposal of Partial Sharing for Link-Sharing Method of Buffer in NoC Router.
CANDAR
Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman
2013 — conf
An Adaptive Routing of the 2-D Torus Network Based on Turn Model.
CANDAR
Yasuyuki Miura, Kazuya Matoyama, Kentaro Shimozono, Shigeyoshi Watanabe
2013 J jnl
Analysis of emission right prices in greenhouse gas emission trading via agent-based model.
Multiagent Grid Syst.
Tomohiro Nakada, Keiki Takadama, Shigeyoshi Watanabe
2013 J jnl
Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Manabu Kobayashi, Hiroshi Ninomiya, Shigeyoshi Watanabe
2013 J jnl
Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroshi Ninomiya, Manabu Kobayashi, Shigeyoshi Watanabe
2010 B conf
Adaptive routing algorithms and implementation for interconnection network TESH for parallel processing.
LCN
Yasuyuki Miura, Masahiro Kaneko, Shigeyoshi Watanabe
2010 J jnl
Foreword.
IEICE Trans. Electron.
Shigeyoshi Watanabe
2010 — conf
Subtractive Color Process for Lossless Compression of Non-photographed Images.
IPCV
Yasuyuki Miura, Masato Suzuki, Ryo Morikawa, Shigeyoshi Watanabe
2008 C conf
A Quantitative Method for Comparing Multi-Agent-Based Simulations in Feature Space.
MABS
Ryota Arai, Shigeyoshi Watanabe
2007 B conf
A Case Study of Applying SNA to Analyze CSCL Social Network.
ICALT
Zuoliang Chen, Shigeyoshi Watanabe
2007 B conf
Comparison of discriminatory pricing and uniform pricing rules in electricity markets using an agent model with risk consideration.
IEEE Congress on Evolutionary Computation
Guilan Zhi, Shigeyoshi Watanabe
2006 — conf
A Fuzzy Model for Bidding Behavior of Participants in Electricity Markets.
ICICIC (2)
Guilan Zhi, Shigeyoshi Watanabe
2006 J jnl
Design of a 128-mb SOI DRAM using the floating body cell (FBC).
IEEE J. Solid State Circuits
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama
2005 — conf
Culture & Motivation: Establishing an International Storytelling Forum.
CELDA
Zuoliang Chen, Shigeyoshi Watanabe
2005 — conf
MASSE: environment supporting for simulation and analysis of multiagent systems.
CTS
Tomomi Takashina, Zhenbo Bi, Ariuna Damba, Guilan Zhi, Kazuhide Tanaka, Hiroki Sayama, Shigeyoshi Watanabe
2005 — conf
Policy Control in Multiagent System.
Computational Intelligence
Ariuna Damba, Shigeyoshi Watanabe
2004 — conf
Intelligent control in dynamic system.
RAM
Ariuna Damba, Shigeyoshi Watanabe
2002 B conf
Individual Level Analysis Using Decision Making Features in Multiagent Based Simulation.
PRIMA
Tomomi Takashina, Kazuhide Tanaka, Shigeyoshi Watanabe
1998 J jnl
Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's.
IEEE J. Solid State Circuits
Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi
1994 J jnl
Offset compensating bit-line sensing scheme for high density DRAM's.
IEEE J. Solid State Circuits
Yohji Watanabe, Nobuo Nakamura, Shigeyoshi Watanabe
1994 J jnl
Open/folded bit-line arrangement for ultra-high-density DRAM's.
IEEE J. Solid State Circuits
Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi
1994 J jnl
Standby/active mode logic for sub-1-V operating ULSI memory.
IEEE J. Solid State Circuits
Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango
1993 J jnl
An experimental DRAM with a NAND-structured cell.
IEEE J. Solid State Circuits
Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Masako Ohta, Shinichiro Shiratake, Takeshi Hamamoto, Takashi Yamada, Masami Aoki, Shigeru Ishibashi, Yukihito Oowaki, Shigeyoshi Watanabe, Fujio Masuoka
1993 J jnl
BiCMOS circuit technology for high-speed DRAMs.
IEEE J. Solid State Circuits
Shigeyoshi Watanabe, Koji Sakui, Tsuneaki Fuse, Takahiko Hara, Seiichi Aritome, Katsuhiko Hieda
1993 J jnl
Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs.
IEEE J. Solid State Circuits
Daisaburo Takashima, Shigeyoshi Watanabe, Tsuneaki Fuse, Kazumasa Sunouchi, Takahiko Hara
1992 J jnl
Word-line architecture for highly reliable 64-Mb DRAM.
IEEE J. Solid State Circuits
Daisaburo Takashima, Yukihito Oowaki, Ryu Ogiwara, Yohji Watanabe, Kenji Tsuchida, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Kazunori Ohuchi
1991 J jnl
A 33-ns 64-Mb DRAM.
IEEE J. Solid State Circuits
Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka
1990 J jnl
The stabilized reference-line (SRL) technique for scaled DRAMs.
IEEE J. Solid State Circuits
Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka
1989 J jnl
A 45-ns 16-Mbit DRAM with triple-well structure.
IEEE J. Solid State Circuits
Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita
1989 J jnl
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.
IEEE J. Solid State Circuits
Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka