Shigetoshi Nakatake

82 papers A 8C 5Misc 1Journal 24Unranked 44

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator. MWSCAS Xuncheng Zou, Shigetoshi Nakatake
2020	—	`conf`	An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation. MOCAST Chao Geng, Qingji Sun, Shigetoshi Nakatake
2020	J	`jnl`	Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks. Sensors Chao Geng, Qingji Sun, Shigetoshi Nakatake
2019	J	`jnl`	A Low Voltage Stochastic Flash ADC without Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Xuncheng Zou, Shigetoshi Nakatake
2019	—	`conf`	An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture. APCCAS Ryosuke Sakai, Shigetoshi Nakatake
2019	J	`jnl`	Density Optimization for Analog Layout Based on Transistor-Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chao Geng, Bo Liu, Shigetoshi Nakatake
2019	—	`conf`	On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing. APCCAS Xinghuai Zhang, Shigetoshi Nakatake
2018	—	`conf`	Analog Retargeting Constraint Extraction Based on Fundamental Circuits and Layout Regularity. NGCAS Xuncheng Zou, Shigetoshi Nakatake
2018	J	`jnl`	Analog perceptron circuit with DAC-based multiplier. Integr. Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake
2018	—	`conf`	Hierarchical Floorplanning Based on Analog Structure Tree. NGCAS Chao Geng, Shigetoshi Nakatake
2018	J	`jnl`	Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenya Kondo, Koichi Tanno, Hiroki Tamura, Shigetoshi Nakatake
2018	—	`conf`	On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing Bridge. MWSCAS Takaaki Shirakawa, Ryosuke Sakai, Shigetoshi Nakatake
2018	J	`jnl`	Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Design Autom. Electr. Syst. Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
2017	—	`conf`	A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends. NGCAS Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake
2017	—	`conf`	Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration. NGCAS Daishi Isogai, Bo Liu, Yoritaka Ishiguchi, Shigetoshi Nakatake
2017	—	`conf`	Explicit layout pattern density controlling based on transistor-array-style. MWSCAS Chao Geng, Bo Liu, Shigetoshi Nakatake
2017	—	`conf`	Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit. ACM Great Lakes Symposium on VLSI Xuncheng Zou, Bo Liu, Shigetoshi Nakatake
2017	A	`conf`	Overview of the 2017 CAD contest at ICCAD: Invited paper. ICCAD Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake
2016	J	`jnl`	A Sensor-Based Data Visualization System for Training Blood Pressure Measurement by Auscultatory Method. IEICE Trans. Inf. Syst. Chooi-Ling Goh, Shigetoshi Nakatake
2016	—	`conf`	A multi-functional memory unit with PLA-based reconfigurable decoder. ReConFig Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen
2016	J	`jnl`	DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. ACM Trans. Design Autom. Electr. Syst. Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang
2016	A	`conf`	Overview of the 2016 CAD contest at ICCAD. ICCAD Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake
2016	—	`conf`	Routability of twisted common-centroid capacitor array under signal coupling constraints. MWSCAS Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang
2016	J	`jnl`	Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Ryoichi Miyauchi, Koichi Tanno, Akihiro Yamada
2016	—	`conf`	Twin-row-style for MOS analog layout. ICECS Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen
2015	J	`jnl`	Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2015	—	`conf`	Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning. ISVLSI Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake
2015	C	`conf`	Subblock-level matching layout for analog block-pair and its manufacturability evaluation. ISCAS Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Koichi Tanno, Akihiro Yamada
2013	—	`conf`	A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. ACM Great Lakes Symposium on VLSI Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake
2013	—	`conf`	A comparator energy model considering shallow trench isolation stress by geometric programming. ISQED Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake
2013	J	`jnl`	Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2013	C	`conf`	Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. VLSI-SoC Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake
2013	—	`conf`	Practicality on placement given by optimality of packing. ISPD Shigetoshi Nakatake
2013	J	`jnl`	Structured Analog Circuit and Layout Design with Transistor Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
2012	C	`conf`	A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. ISCAS Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue
2012	—	`conf`	CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. ISQED Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake
2012	J	`jnl`	Layout-Aware Variability Characterization of CMOS Current Sources. IEICE Trans. Electron. Bo Liu, Bo Yang, Shigetoshi Nakatake
2012	—	`conf`	Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. ISQED Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake
2011	—	`conf`	Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. ISQED Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2011	—	`conf`	Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. ACM Great Lakes Symposium on VLSI Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake
2010	—	`conf`	D-A converter based variation analysis for analog layout design. ASP-DAC Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake
2010	J	`jnl`	Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kokoro Kato, Masakazu Endo, Tadao Inoue, Shigetoshi Nakatake, Masaki Yamabe, Sunao Ishihara
2010	C	`conf`	Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. ISCAS Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake
2010	J	`jnl`	Regularity-Oriented Analog Placement with Conditional Design Rules. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki
2010	—	`conf`	Regularity-oriented analog placement with diffusion sharing and well island generation. ASP-DAC Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki
2010	A	`conf`	Structured analog circuit design and MOS transistor decomposition for high accuracy applications. ICCAD Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
2009	J	`jnl`	Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Bo Yang, Shigetoshi Nakatake
2009	J	`jnl`	Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2009	—	`conf`	Incremental buffer insertion and module resizing algorithm using geometric programming. ACM Great Lakes Symposium on VLSI Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
2009	—	`conf`	STI stress aware placement optimization based on geometric programming. ACM Great Lakes Symposium on VLSI Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake
2009	J	`jnl`	Structured Placement with Topological Regularity Evaluation. IPSJ Trans. Syst. LSI Des. Methodol. Qing Dong, Shigetoshi Nakatake
2008	J	`jnl`	A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Bo Yang, Hiroshi Murata, Shigetoshi Nakatake
2008	—	`conf`	Constraint-free analog placement with topological symmetry structure. ASP-DAC Qing Dong, Shigetoshi Nakatake
2008	—	`conf`	Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. ISQED Bo Yang, Shigetoshi Nakatake, Hiroshi Murata
2008	C	`conf`	Transistor-level programmable MOS analog IC with body biasing. ISCAS Toru Fujimura, Shigetoshi Nakatake
2007	—	`conf`	Block placement to ensure channel routability. ACM Great Lakes Symposium on VLSI Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh
2007	—	`conf`	Structured Placement with Topological Regularity Evaluation. ASP-DAC Shigetoshi Nakatake
2006	—	`conf`	Adaptive Porting of Analog IPs with Reusable Conservative Properties. ISVLSI Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani
2006	—	`conf`	Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. ISVLSI Tan Yan, Shigetoshi Nakatake, Takashi Nojima
2006	—	`conf`	Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. ISVLSI Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake
2006	—	`conf`	Sequence-Pair Based Compaction under Equi-Length Constraint. APCCAS Keiji Kida, Takehiko Matsuo, Tetsuya Tashiro, Shigetoshi Nakatake
2006	J	`jnl`	The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2005	—	`conf`	The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2004	—	`conf`	A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
2004	—	`conf`	A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. ISCAS (4) Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake
2004	—	`conf`	Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
2004	—	`conf`	Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
2003	J	`jnl`	An Incremental Wiring Algorithm for VLSI Layout Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2002	—	`conf`	Chip size estimation based on wiring area. APCCAS (2) Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2002	J	`jnl`	Consistent floorplanning with hierarchical superconstraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
2002	—	`conf`	Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. ASP-DAC/VLSI Design Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
2001	—	`conf`	Consistent floorplanning with super hierarchical constraints. ISPD Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
2000	Misc	`conf`	Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake
2000	—	`conf`	Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
1998	—	`conf`	Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. ASP-DAC Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani
1998	J	`jnl`	Module packing based on the BSG-structure and IC layout applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
1998	A	`conf`	The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita
1998	A	`conf`	The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani
1996	A	`conf`	Module placement on BSG-structure and IC layout applications. ICCAD Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
1996	J	`jnl`	VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
1995	A	`conf`	Rectangle-packing-based module placement. ICCAD Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
1994	A	`conf`	Channel-driven global routing with consistent placement (extended abstract). ICCAD Shigetoshi Nakatake, Yoji Kajitani