Shigeru Yamashita

148 papers A* 3A 11B 7C 16Misc 15Journal 57Unranked 39

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	A Polynomial Time Routing Algorithm for Meda Biochips Based on Dijkstra's Algorithm. VLSID Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama, Ankur Guputa
2026	—	`conf`	Accessible Ratio-Specific Mixing: Single-Pressure-Driven Multi-Reagent Mixer Design and Synthesis for 3D-Printed Microfluidics. ASP-DAC Yushen Zhang, Debraj Kundu, Tsun-Ming Tseng, Sudip Roy, Shigeru Yamashita, Ulf Schlichtmann
2025	—	`conf`	A Decomposition Method for MCT Gates Considering T-depth of Each Qubit. ISVLSI Zanhe Qi, Kouki Hirono, David Clarino, Shigeru Yamashita
2025	J	`jnl`	Leveraging Different Boolean Function Decompositions to Reduce T-Count in LUT-Based Quantum Circuit Synthesis. IEICE Trans. Inf. Syst. David Clarino, Naoya Asada, Atsushi Matsuo, Shigeru Yamashita
2025	A	`conf`	Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device. DATE Debraj Kundu, Tsun-Ming Tseng, Shigeru Yamashita, Ulf Schlichtmann
2025	B	`conf`	Poster: A Comparative Analysis of Machine Learning Models for SAT Runtime Prediction. RTCSA Tomohisa Kawakami, Tomoyasu Shimada, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita
2025	—	`conf`	Realizing 4-input Functions with the Minimum Toffoli Gate Count. ISMVL Shigeru Yamashita, Takashi Horiyama, Norihito Yasuda, Tatsuya Nakao
2025	J	`jnl`	Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. David Clarino, Shohei Kuroda, Shigeru Yamashita
2024	—	`conf`	An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips. ISOCC Kensuke Fukui, Shigeru Yamashita
2024	—	`conf`	An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels. ISOCC Suzuki Koki, Shigeru Yamashita
2024	J	`jnl`	Efficient Realization of an SC Circuit with Feedback and Its Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuto Arimura, Shigeru Yamashita
2024	A*	`conf`	Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip. DAC Zhidan Zheng, Liaoyuan Cheng, Kanta Arisawa, Qingyu Li, Alexandre Truppel, Shigeru Yamashita, Tsun-Ming Tseng, Ulf Schlichtmann
2024	Misc	`conf`	Optimization for Gaussian Elimination-Based NNA-Compliant Circuit Synthesis Method by Inserting CN OT Gates. QCE Zanhe Qi, Atsushi Matsuo, Shigeru Yamashita
2024	B	`conf`	Optimizing Decision Diagrams for Measurements of Quantum Circuits. ASPDAC Ryosuke Matsuo, Rudy Raymond, Shigeru Yamashita, Shin-ichi Minato
2024	—	`conf`	Simultaneous Routing with Washing Droplets in MEDA Biochips. ATAIT Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita
2024	Misc	`conf`	Utilizing Don't-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits. QCE David Clarino, Kyouhei Seino, Atsushi Matsuo, Shigeru Yamashita
2023	J	`jnl`	A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips. Sensors Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita
2023	—	`conf`	A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs. NEWCAS Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita
2023	—	`conf`	A Fast Approach to Droplet Routing with Shape-Dependent Velocity on MEDA Biochips. NEWCAS Kaito Mori, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita
2023	J	`jnl`	A SAT Approach to the Initial Mapping Problem in SWAP Gate Insertion for Commuting Gates. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsushi Matsuo, Shigeru Yamashita, Daniel J. Egger
2023	J	`jnl`	An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita
2023	—	`conf`	An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates. ASP-DAC Kyohei Seino, Shigeru Yamashita
2023	J	`jnl`	Enhancing VQE Convergence for Optimization Problems with Problem-Specific Parameterized Quantum Circuits. IEICE Trans. Inf. Syst. Atsushi Matsuo, Yudai Suzuki, Ikko Hamamura, Shigeru Yamashita
2023	J	`jnl`	Making General Dilution Graphs Robust to Unbalanced-Split Errors on Digital Microfluidic Biochips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ikuru Yoshida, Shigeru Yamashita
2023	C	`conf`	Minimizing the Impact of Unbalanced Splitting Errors on DMFBs Without Any Overhead. DSD Yuji Wada, Shigeru Yamashita
2023	—	`conf`	Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips. ICEIC Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita
2023	A	`conf`	Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations. ICCAD David Clarino, Naoya Asada, Shigeru Yamashita
2023	J	`jnl`	Preparing Fluid Samples Under Retention Time Constraints Using Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debraj Kundu, Venkata Lavanya Sarvasiddi, Sukanta Bhattacharjee, Shigeru Yamashita, Sudip Roy
2023	Misc	`conf`	Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices. VLSID Masataka Hirai, Debraj Kundu, Shigeru Yamashita, Sudip Roy, Hiroyuki Tomiyama
2023	—	`conf`	Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits. ISMVL David Clarino, Shohei Kuroda, Shigeru Yamashita
2022	J	`jnl`	Approximating stochastic numbers to reduce latency. it Inf. Technol. Syoki Kawaminami, Yukino Watanabe, Shigeru Yamashita
2022	J	`jnl`	Mixer-Based Washing Methods for Programmable Microfluidic Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yifang Bao, Shigeru Yamashita, Bing Li, Tsung-Yi Ho
2022	C	`conf`	Optimization of Quantum Boolean Circuits by Relative-Phase Toffoli Gates. RC Shohei Kuroda, Shigeru Yamashita
2022	J	`jnl`	Shape-Dependent Velocity Based Droplet Routing on MEDA Biochips. IEEE Access Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, Sudip Roy
2021	Misc	`conf`	A Multiply Accumulator for Stochastic Numbers Without Scaling Errors. VLSID Katsuhiro Ichikawa, Shigeru Yamashita
2021	C	`conf`	Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip. DSD Shuaijie Ying, Sudip Roy, Juinn-Dar Huang, Shigeru Yamashita
2021	—	`conf`	Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures. ASP-DAC Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita
2021	J	`jnl`	Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution. Integr. Debraj Kundu, Jitendra Giri, Sataru Maruyama, Sudip Roy, Shigeru Yamashita
2021	—	`conf`	Minimization of Routing Area in MEDA Biochips. BioCAS Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita
2021	C	`ed.`	Reversible Computation - 13th International Conference, RC 2021, Virtual Event, July 7-8, 2021, Proceedings RC Shigeru Yamashita, Tetsuo Yokoyama
2021	—	`conf`	Triple-Rail Stochastic Number and Its Applications. ISOCC Shoki Kawaminami, Shigeru Yamashita
2020	J	`jnl`	Editorial for the special issue on disruptive computing technologies. CCF Trans. High Perform. Comput. Yiran Chen, Deliang Fan, Yanzhi Wang, Shigeru Yamashita
2020	J	`jnl`	Efficient Methods to Generate Constant SNs with Considering Trade-Off between Error and Overhead and Its Evaluation. IEICE Trans. Inf. Syst. Yudai Sakamoto, Shigeru Yamashita
2020	J	`jnl`	Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jingwen Ding, Shigeru Yamashita
2020	—	`conf`	Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution. ASP-DAC Satoru Maruyama, Debraj Kundu, Shigeru Yamashita, Sudip Roy
2020	—	`conf`	Reducing T-count When Decomposing Many MPMCT Gates Simultaneously. ISMVL Soma Esaki, Shigeru Yamashita
2020	A	`conf`	Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. DATE Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann, Sudip Roy
2019	C	`conf`	An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid. RC Atsushi Matsuo, Shigeru Yamashita
2019	J	`jnl`	Compaction of Topological Quantum Circuits by Modularization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kota Asai, Shigeru Yamashita
2019	J	`jnl`	Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips. ACM Trans. Design Autom. Electr. Syst. Ankur Gupta, Juinn-Dar Huang, Shigeru Yamashita, Sudip Roy
2019	J	`jnl`	Mapping a Quantum Circuit to 2D Nearest Neighbor Architecture by Changing the Gate Order. IEICE Trans. Inf. Syst. Wakaki Hattori, Shigeru Yamashita
2019	—	`conf`	Maximum Error-Aware Design of Approximate Array Multipliers. ISOCC Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, Hiroyuki Tomiyama
2019	—	`conf`	Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models. VLSI-DAT Kang-Yi Fan, Shigeru Yamashita, Juinn-Dar Huang
2019	C	`conf`	Reducing the Overhead of Mapping Quantum Circuits to IBM Q System. ISCAS Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita
2019	Misc	`conf`	Reducing the Overhead of Stochastic Number Generators Without Increasing Error. VLSID Yudai Sakamoto, Shigeru Yamashita
2019	J	`jnl`	Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita
2018	J	`jnl`	Logical Qubit Layout Problem for ICM Representation. J. Inf. Process. Nurul Ain Binti Adnan, Shigeru Yamashita
2018	C	`conf`	Quantum Circuit Optimization by Changing the Gate Order for 2D Nearest Neighbor Architectures. RC Wakaki Hattori, Shigeru Yamashita
2017	J	`jnl`	A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
2017	J	`jnl`	Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1). NII Shonan Meet. Rep. Shigeru Yamashita, Tsung-Yi Ho, Robert Wille, Krishnendu Chakrabarty
2017	J	`jnl`	Reduction of Quantum Cost by Making Temporary Changes to the Function. IEICE Trans. Inf. Syst. Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mishchenko
2017	J	`jnl`	Stochastic Number Generation with the Minimum Inputs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ritsuko Muguruma, Shigeru Yamashita
2016	J	`jnl`	A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
2016	C	`conf`	A pre-optimization technique to generate initial reversible circuits with low quantum cost. ISCAS Nurul Ain Binti Adnan, Kouhei Kushida, Shigeru Yamashita
2016	—	`conf`	A systematic methodology for design and analysis of approximate array multipliers. APCCAS Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
2016	J	`jnl`	Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders. CoRR P. Balasubramanian, Shigeru Yamashita
2016	Misc	`conf`	Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences. VLSID Tsung-Yi Ho, Shigeru Yamashita, Ansuman Banerjee, Sudip Roy
2016	A	`conf`	Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. DATE Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita
2016	Misc	`conf`	ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips. VLSID Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa, Shigeru Yamashita
2016	J	`jnl`	Quantum Query Complexity of Almost All Functions with Fixed On-set Size. Comput. Complex. Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita
2016	Misc	`conf`	Stochastic Number Generation with Few Inputs. VLSID Ritsuko Muguruma, Shigeru Yamashita
2015	A	`conf`	A general testing method for digital microfluidic biochips under physical constraints. ITC Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty
2015	J	`jnl`	An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
2015	B	`conf`	Testing of digital microfluidic biochips with arbitrary layouts. ETS Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty
2014	C	`conf`	2D Qubit Layout Optimization for Topological Quantum Computation. RC Nurul Ain Binti Adnan, Shigeru Yamashita, Simon J. Devitt, Kae Nemoto
2014	A	`conf`	A logic integrated optimal pin-count design for digital microfluidic biochips. DATE Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
2014	—	`conf`	A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips. ASP-DAC Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho
2014	J	`jnl`	An Energy-Efficient Patchable Accelerator and Its Design Methods. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Yoshida, Masayuki Wakizaka, Shigeru Yamashita, Masahiro Fujita
2014	Misc	`conf`	Better-Than-DMR Techniques for Yield Improvement. FCCM Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima
2014	C	`ed.`	Reversible Computation - 6th International Conference, RC 2014, Kyoto, Japan, July 10-11, 2014. Proceedings RC Shigeru Yamashita, Shin-ichi Minato
2013	—	`conf`	A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips. ASP-DAC Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi
2013	J	`jnl`	Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi
2013	C	`conf`	On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design. PRDC P. Balasubramanian, Shigeru Yamashita
2013	J	`jnl`	Selective Check of Data-Path for Effective Fault Tolerance. IEICE Trans. Inf. Syst. Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima
2013	J	`jnl`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. IEICE Trans. Inf. Syst. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	—	`conf`	A redundant wire addition method for Patchable Accelerator. ICECS Masayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi, Shigeru Yamashita
2012	—	`conf`	An Optimization Problem for Topological Quantum Computation. Asian Test Symposium Shigeru Yamashita
2012	—	`conf`	On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita
2012	J	`jnl`	Quantum Walks on the Line with Phase Parameters. IEICE Trans. Inf. Syst. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	J	`jnl`	Reconstructing Strings from Substrings with Quantum Queries CoRR Richard Cleve, Kazuo Iwama, François Le Gall, Harumichi Nishimura, Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita
2012	—	`conf`	Reconstructing Strings from Substrings with Quantum Queries. SWAT Richard Cleve, Kazuo Iwama, François Le Gall, Harumichi Nishimura, Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita
2012	J	`jnl`	Synthesis of Semi-Classical Quantum Circuits. J. Multiple Valued Log. Soft Comput. Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
2012	J	`jnl`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication CoRR Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	C	`conf`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. TAMC Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2012	J	`jnl`	Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. Electron. Colloquium Comput. Complex. Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2011	Misc	`conf`	An efficient algorithm for constructing a Sequence Binary Decision Diagram representing a set of reversed sequences. GrC Hiroshi Aoki, Shigeru Yamashita, Shin-ichi Minato
2011	J	`jnl`	An efficient conversion of quantum circuits to a linear nearest neighbor architecture. Quantum Inf. Comput. Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2011	C	`conf`	Changing the Gate Order for Optimal LNN Conversion. RC Atsushi Matsuo, Shigeru Yamashita
2010	C	`conf`	An Evaluation of "Face-to-Face" Group Activity on Blended-Learning in University Cooperation. ICCE Yuki Mori, Shohei Shimada, Tetsuo Suemoto, Shigeru Yamashita, Shigeto Ozawa
2010	J	`jnl`	Fast equivalence - checking for quantum circuits. Quantum Inf. Comput. Shigeru Yamashita, Igor L. Markov
2010	—	`conf`	Fast equivalence-checking for quantum circuits. NANOARCH Shigeru Yamashita, Igor L. Markov
2009	J	`jnl`	Average/Worst-Case Gap of Quantum Query Complexities by On-Set Size CoRR Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita
2009	J	`jnl`	Fast Equivalence-checking for Quantum Circuits. CoRR Shigeru Yamashita, Igor L. Markov
2009	J	`jnl`	Multi-Party Quantum Communication Complexity with Routed Messages. IEICE Trans. Inf. Syst. Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita
2009	J	`jnl`	Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition. Quantum Inf. Comput. Yumi Nakajima, Yasuhito Kawano, Hiroshi Sekigawa, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2008	C	`conf`	A Functional Unit with Small Variety of Highly Reliable Cells. PRDC Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2008	C	`conf`	An efficient verification of quantum circuits under a practical restriction. CIT Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
2008	J	`jnl`	DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller
2008	Misc	`conf`	Multi-party Quantum Communication Complexity with Routed Messages. COCOON Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita
2008	—	`conf`	Polynomial-Time Construction of Linear Network Coding. ICALP (1) Kazuo Iwama, Harumichi Nishimura, Mike Paterson, Rudy Raymond, Shigeru Yamashita
2008	B	`conf`	Quantum Query Complexity of Boolean Functions with Small On-Sets. ISAAC Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita
2007	—	`conf`	A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. ARC Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima
2007	B	`conf`	A practical framework to utilize quantum search. IEEE Congress on Evolutionary Computation Shigeru Yamashita, Masaki Nakanishi
2007	J	`jnl`	Improved algorithms for quantum identification of Boolean oracles. Theor. Comput. Sci. Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Rudy Raymond, Shigeru Yamashita
2007	A	`conf`	Quantum Network Coding. STACS Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond Harry Putra, Shigeru Yamashita
2007	J	`jnl`	Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles. IEICE Trans. Inf. Syst. Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe
2007	B	`conf`	Unbounded-Error Classical and Quantum Communication Complexity. ISAAC Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita
2007	A*	`conf`	Unbounded-Error One-Way Classical and Quantum Communication Complexity. ICALP Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita
2006	B	`conf`	(4, 1)-Quantum Random Access Coding Does Not Exist. ISIT Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita
2006	Misc	`conf`	A New Approach to Online FPGA Placement. CISS Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe
2006	—	`conf`	A transduction-based framework to synthesize RSFQ circuits. ASP-DAC Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi
2006	J	`jnl`	An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe
2006	—	`conf`	Improved Algorithms for Quantum Identification of Boolean Oracles. SWAT Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Rudy Raymond Harry Putra, Shigeru Yamashita
2006	J	`jnl`	Quantum Biased Oracles. Inf. Media Technol. Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita
2006	—	`conf`	Quantum Network Coding. Complexity of Boolean Functions Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita
2006	J	`jnl`	Quantum lower bounds for the Goldreich-Levin problem. Inf. Process. Lett. Mark Adcock, Richard Cleve, Kazuo Iwama, Raymond H. Putra, Shigeru Yamashita
2006	Misc	`conf`	Robust Quantum Algorithms with COCOON Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe
2005	—	`conf`	Event-oriented computing with reconfigurable platform. ASP-DAC Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita
2005	J	`jnl`	Quantum Sampling for Balanced Allocations. IEICE Trans. Inf. Syst. Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita
2005	—	`conf`	Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. ERSA Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe
2005	J	`jnl`	SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
2004	A	`conf`	Quantum Identification of Boolean Oracles. STACS Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Hiroyuki Masuda, Raymond H. Putra, Shigeru Yamashita
2004	—	`conf`	SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. ACM Great Lakes Symposium on VLSI Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
2004	A	`conf`	SPFD-based one-to-many rewiring. FPGA Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
2003	J	`jnl`	Efficient Algorithms for NMR Quantum Computers with Small Qubits. New Gener. Comput. Noboru Kunihiro, Shigeru Yamashita
2003	Misc	`conf`	Quantum Sampling for Balanced Allocations. COCOON Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita
2003	J	`jnl`	Transformation Rules for CNOT-based Quantum Circuits and Their Applications. New Gener. Comput. Kazuo Iwama, Shigeru Yamashita
2002	A*	`conf`	Transformation rules for designing CNOT-based quantum circuits. DAC Kazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita
2000	—	`conf`	An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. ASP-DAC Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
2000	J	`jnl`	SPFD: A new method to express functional flexibility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1999	—	`conf`	An Integrated Approach for Synthesizing LUT Networks. Great Lakes Symposium on VLSI Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1998	—	`conf`	New Methods to Find Optimal Non-Disjoint Bi-Decompositions. ASP-DAC Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1998	A	`conf`	Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. DATE Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
1997	—	`conf`	Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. Great Lakes Symposium on VLSI Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
1996	A	`conf`	A new method to express functional permissibilities for LUT based FPGAs and its applications. ICCAD Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1996	J	`jnl`	Design of logic circuits with wired-logic utilizing transduction method. Syst. Comput. Jpn. Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
1996	J	`jnl`	Optimization methods for look-up table-type FPGAs based on permissible functions. Syst. Comput. Jpn. Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
1995	—	`conf`	Optimization methods for lookup-table-based FPGAs using transduction method. ASP-DAC Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga