Shigeru Oyanagi

26 papers A 1B 2C 3Misc 4Journal 10Unranked 6
YearRankTypeTitle / Venue / Authors
2018 J jnl
Underwater-Drone With Panoramic Camera for Automatic Fish Recognition Based on Deep Learning.
IEEE Access
Lin Meng, Takuma Hirayama, Shigeru Oyanagi
2017 — conf
The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource Hardware.
IIKI
Lin Meng, Takuma Hirayama, Shigeru Oyanagi
2013 J jnl
A Real-Time Burst Analysis Method.
Int. J. Artif. Intell. Tools
Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi
2012 J jnl
Hybrid MPI-OpenMP Paradigm on SMP Clusters: MPEG-2 Encoder and N-Body Simulation
CoRR
Truong Vinh Truong Duy, Katsuhiro Yamazaki, Kosai Ikegami, Shigeru Oyanagi
2012 J jnl
Performance Evaluation of Treecode Algorithm for N-Body Simulation Using GridRPC System
CoRR
Truong Vinh Truong Duy, Katsuhiro Yamazaki, Shigeru Oyanagi
2011 B conf
A Real-Time Burst Detection Method.
ICTAI
Ryohei Ebina, Kenji Nakamura, Shigeru Oyanagi
2011 — conf
An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation.
ARCS
Son Truong Nguyen, Shigeru Oyanagi
2011 Misc conf
An Input Buffer Architecture for On-chip Routers.
ICNC
Chu Van Thiem, Shigeru Oyanagi
2010 C conf
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks.
DSD
Son Truong Nguyen, Shigeru Oyanagi
2010 Misc conf
Control Independence Using Dual Renaming.
ICNC
Lin Meng, Shigeru Oyanagi
2010 Misc conf
The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers.
ICNC
Son Truong Nguyen, Shigeru Oyanagi
2009 J jnl
Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate.
IEICE Trans. Inf. Syst.
Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
2008 Misc conf
Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding.
FCCM
Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
2008 B conf
Three-stage pipeline implementation for SHA2 using data forwarding.
FPL
Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
2006 C conf
ExMiner: An Efficient Algorithm for Mining Top-K Frequent Patterns.
ADMA
Quang Tran Minh, Shigeru Oyanagi, Katsuhiro Yamazaki
2006 C conf
Mining the K-Most Interesting Frequent Patterns Sequentially.
IDEAL
Quang Tran Minh, Shigeru Oyanagi, Katsuhiro Yamazaki
2004 J jnl
Speculative Selection Routing in 2D Torus Network.
IEICE Trans. Inf. Syst.
Tran Cong So, Shigeru Oyanagi, Katsuhiro Yamazaki
2002 — conf
Mining WWW Access Sequence by Matrix Clustering.
WebKDD
Shigeru Oyanagi, Kazuto Kubota, Akihiko Nakase
2001 A conf
Implementation and performance evaluation of dynamic scheduling for parallel decision tree generation.
IPDPS
Kazuto Kubota, Akihiko Nakase, Shigeru Oyanagi
1996 J jnl
Improving the performance of global communication on a three-dimensional torus network.
Syst. Comput. Jpn.
Yasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi
1994 — conf
Improving the Performance of Global Communication on a 3D torus network.
ICPP (3)
Yasushi Kawakura, Shigeru Oyanagi
1992 J jnl
Implementation of the prodigy parallel AI machine and performance evaluation of communication.
Syst. Comput. Jpn.
Noboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi
1991 — conf
Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY.
ICPP (1)
Noboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi
1989 J jnl
Network Performance of the Prodigy Parallel AI Machine.
Syst. Comput. Jpn.
Takashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi
1980 J jnl
A Dynamically Microprogammable Computer with Low-Level Parallelism.
IEEE Trans. Computers
Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama
1977 — conf
Hardware Organization of a Low Level Parallel Processor.
IFIP Congress
Shinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara