Shigeru Atsumi

11 papers Journal 11

Year	Rank	Type	Title / Venue / Authors
2002	J	`jnl`	A 44-mm IEEE J. Solid State Circuits Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi
2002	J	`jnl`	High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. IEEE J. Solid State Circuits Toru Tanzawa, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi
2001	J	`jnl`	Wordline voltage generating system for low-power low-voltage flash memories. IEEE J. Solid State Circuits Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi
2000	J	`jnl`	A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. IEEE J. Solid State Circuits Shigeru Atsumi, Akira Umezawa, Toru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe
2000	J	`jnl`	Design of a sense circuit for low-voltage flash memories. IEEE J. Solid State Circuits Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi
1999	J	`jnl`	A CMOS bandgap reference circuit with sub-1-V operation. IEEE J. Solid State Circuits Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui
1999	J	`jnl`	Optimization of word-line booster circuits for low-voltage flash memories. IEEE J. Solid State Circuits Toru Tanzawa, Shigeru Atsumi
1994	J	`jnl`	A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. IEEE J. Solid State Circuits Shigeru Atsumi, Masao Kuriyama, Akira Umezawa, Hironori Banba, Kiyomi Naruke, Seiji Yamada, Yoichi Ohshima, Masamitsu Oshikiri, Yohei Hiura, Tomoko Yamane, Kuniyoshi Yoshikawa
1992	J	`jnl`	A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure. IEEE J. Solid State Circuits Akira Umezawa, Shigeru Atsumi, Masao Kuriyama, Hironori Banba, Ken-ichi Imamiya, Kiyomi Naruke, Seiji Yamada, Etsushi Obi, Masamitsu Oshikiri, Tomoko Suzuki, Sumio Tanaka
1990	J	`jnl`	A 16-ns 1-Mb CMOS EPROM. IEEE J. Solid State Circuits Masao Kuriyama, Shigeru Atsumi, Ken-ichi Imamiya, Yumiko Iyama, Naohiro Matsukawa, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Sumio Tanaka
1990	J	`jnl`	A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. IEEE J. Solid State Circuits Kenichi Imamiya, Jun-ichi Miyamoto, Shigeru Atsumi, Nobuaki Ohtsuka, Yukinori Muroya, Toshiyuki Sako, Masao Higashino, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Hitoshi Araki, Yukio Kaneko, Kazuhito Narita, Norihisa Arai, Kuniyoshi Yoshikawa, Shinichi Tanaka