Shigeki Tomishima

14 papers A 1Journal 10Unranked 3

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Enabling Homomorphically Encrypted Inference for Large DNN Models. IEEE Trans. Computers Guillermo Lloret-Talavera, Marc Jordà, Harald Servat, Fabian Boemer, Chetan Chauhan, Shigeki Tomishima, Nilesh N. Shah, Antonio J. Peña
2021	J	`jnl`	Enabling Homomorphically Encrypted Inference for Large DNN Models. CoRR Guillermo Lloret-Talavera, Marc Jordà, Harald Servat, Fabian Boemer, Chetan Chauhan, Shigeki Tomishima, Nilesh N. Shah, Antonio J. Peña
2017	—	`conf`	23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu
2015	J	`jnl`	A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. IEEE J. Solid State Circuits Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang
2015	—	`conf`	A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu
2014	—	`conf`	13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. ISSCC Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang
2002	J	`jnl`	0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. IEEE J. Solid State Circuits Hirohito Kikukawa, Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Shouji Sakamoto, Masatoshi Ishikawa, Wataru Abe, Hiroaki Tanizaki, Hiroshi Kato, Toshitaka Uchikoba, Toshihiro Inokuchi, Manabu Senoh, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Akinori Shibayama, Tsukasa Ooishi, Kazunari Takahashi, Hideto Hidaka
2002	A	`conf`	A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. ITC Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo
2001	J	`jnl`	A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. IEEE J. Solid State Circuits Shigeki Tomishima, Takaharu Tsuji, Toshiaki Kawasaki, Masatoshi Ishikawa, Toshihiro Inokuchi, Hiroshi Kato, Hiroaki Tanizaki, Wataru Abe, Akinori Shibayama, Yoshifumi Fukushima, Mitsutaka Niiro, Masanao Maruta, Toshitaka Uchikoba, Manabu Senoh, Shouji Sakamoto, Tsukasa Ooishi, Hirohito Kikukawa, Hideto Hidaka, Kazunari Takahashi
1999	J	`jnl`	A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada
1996	J	`jnl`	SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto
1995	J	`jnl`	Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto
1994	J	`jnl`	A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1994	J	`jnl`	An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara