Shien-Chun Luo

13 papers C 3Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2022 — conf
Configurable Deep Learning Accelerator with Bitwise-accurate Training and Verification.
VLSI-DAT
Shien-Chun Luo, Kuo-Chiang Chang, Po-Wei Chen, Zhao-Hong Chen
2019 — conf
Customization of a Deep Learning Accelerator.
VLSI-DAT
Shien-Chun Luo
2018 — conf
MORAS: An energy-scalable system using adaptive voltage scaling.
VLSI-DAT
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Jia-Hung Peng, Yuan-Hua Chu
2014 J jnl
A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu
2014 C conf
An ultra-low voltage hearing aid chip using variable-latency design technique.
ISCAS
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
2014 — conf
An ultra-low-power adaptive-body-bias control for subthreshold circuits.
VLSI-DAT
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
2014 J jnl
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.
IEEE Trans. Circuits Syst. II Express Briefs
Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu
2013 — conf
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.
ISSCC
Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang
2013 J jnl
An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library.
IEEE Trans. Circuits Syst. II Express Briefs
Shien-Chun Luo, Ching-Ji Huang, Yuan-Hua Chu
2012 C conf
Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion.
ISCAS
Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou
2010 J jnl
A Sub-200-mV Voltage-Scalable SRAM With Tolerance of Access Failure by Self-Activated Bitline Sensing.
IEEE Trans. Circuits Syst. II Express Briefs
Shien-Chun Luo, Lih-Yih Chiou
2009 J jnl
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics.
IEEE Trans. Very Large Scale Integr. Syst.
Lih-Yih Chiou, Shien-Chun Luo
2007 C conf
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.
ISCAS
Lih-Yih Chiou, Shien-Chun Luo