Shidhartha Das

72 papers A* 9A 11B 2C 4Misc 1Journal 26Unranked 18

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Amir Amirkhany, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito
2022	J	`jnl`	ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator. IEEE Micro Chuteng Zhou, Fernando García-Redondo, Julian Büchel, Irem Boybat, Xavier Timoneda Comas, S. R. Nandakumar, Shidhartha Das, Abu Sebastian, Manuel Le Gallo, Paul N. Whatmough
2022	—	`conf`	SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components. DCIS Fernando García-Redondo, Ali BanaGozar, Kanishkan Vadivel, Henk Corporaal, Shidhartha Das
2022	—	`conf`	SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator. DCIS Kanishkan Vadivel, Fernando García-Redondo, Ali BanaGozar, Henk Corporaal, Shidhartha Das
2022	—	`conf`	System technology co-optimization and design challenges for 3D IC. CICC Supreet Jeloka, Brian Cline, Shidhartha Das, Benoit Labbe, Alejandro Rico, Rainer Herberholz, Javier A. DeLaCruz, Rahul Mathur, Shawn Hung
2021	J	`jnl`	A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs. CoRR George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Greg Favor, Kumar Sankaran, Shidhartha Das
2021	A*	`conf`	APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. MICRO Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das
2021	J	`jnl`	AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator. CoRR Chuteng Zhou, Fernando García-Redondo, Julian Büchel, Irem Boybat, Xavier Timoneda Comas, S. R. Nandakumar, Shidhartha Das, Abu Sebastian, Manuel Le Gallo, Paul N. Whatmough
2021	J	`jnl`	Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization. IEEE Trans. Computers Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
2021	A	`conf`	Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. ISLPED Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim
2021	—	`conf`	Session 4 Overview: Processors Digital Architectures and Systems Subcommittee. ISSCC Sanu Mathew, Shidhartha Das, Hugh Mair
2020	—	`conf`	A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm VLSI Circuits Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das
2020	J	`jnl`	A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration. IEEE J. Solid State Circuits Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2020	J	`jnl`	Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric
2020	B	`conf`	Training DNN IoT Applications for Deployment On Analog NVM Crossbars. IJCNN Fernando García-Redondo, Shidhartha Das, Glen Rosendale
2019	—	`conf`	A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration. ESSCIRC Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das
2019	A	`conf`	A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration. ISLPED Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019	—	`conf`	A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics. BioCAS Matthew Douthwaite, Fernando García-Redondo, Pantelis Georgiou, Shidhartha Das
2019	A	`conf`	Applications of Computation-In-Memory Architectures based on Memristive Devices. DATE Said Hamdioui, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Abu Sebastian, Manuel Le Gallo, Sandeep Pande, Siebren Schaafsma, Francky Catthoor, Shidhartha Das, Fernando García-Redondo, Geethan Karunaratne, Abbas Rahimi, Luca Benini
2019	A	`conf`	CoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs. DATE Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019	J	`jnl`	Design and Optimization of Inductive-Coupling Links for 3-D-ICs. IEEE Trans. Very Large Scale Integr. Syst. Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019	B	`conf`	GeST: An Automatic Framework For Generating CPU Stress-Tests. ISPASS Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides
2019	J	`jnl`	Neural Network Design for Energy-Autonomous AI Applications using Temporal Encoding. CoRR Sergey Mileiko, Thanasin Bunnam, Fei Xia, Rishad A. Shafik, Alex Yakovlev, Shidhartha Das
2019	C	`conf`	Run-time Detection and Mitigation of Power-Noise Viruses. IOLTS Vasileios Tenentes, Shidhartha Das, Daniele Rossi, Bashir M. Al-Hashimi
2019	J	`jnl`	System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2019	J	`jnl`	Training DNN IoT Applications for Deployment On Analog NVM Crossbars. CoRR Fernando García-Redondo, Shidhartha Das, Glen Rosendale
2018	A	`conf`	A high-speed design methodology for inductive coupling links in 3D-ICs. DATE Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2018	A	`conf`	An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. DATE Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Pérez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das
2018	A*	`conf`	Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. MICRO Emre Ozer, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton
2018	J	`jnl`	Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Andrea Bevilacqua, Shidhartha Das, Pieter Harpe
2018	A*	`conf`	Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. MICRO Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
2018	A	`conf`	Low-power 3D integration using inductive coupling links for neurotechnology applications. DATE Benjamin J. Fletcher, Shidhartha Das, Chi-Sang Poon, Terrence S. T. Mak
2018	—	`conf`	Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. DSN Workshops Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo
2018	J	`jnl`	Real-Power Computing. IEEE Trans. Computers Rishad A. Shafik, Alex Yakovlev, Shidhartha Das
2018	J	`jnl`	Sensing CPU Voltage Noise Through Electromagnetic Emanations. IEEE Comput. Archit. Lett. Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
2018	J	`jnl`	Significance-Driven Logic Compression for Energy-Efficient Multiplier Design. IEEE J. Emerg. Sel. Topics Circuits Syst. Issa Qiqieh, Rishad A. Shafik, Ghaith Tarawneh, Danil Sokolov, Shidhartha Das, Alexandre Yakovlev
2017	—	`conf`	Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression. SiPS Issa Qiqieh, Rishad A. Shafik, Ghaith Tarawneh, Danil Sokolov, Shidhartha Das, Alex Yakovlev
2017	J	`jnl`	Error-Resilient Server Ecosystems for Edge and Cloud Datacenters. Computer Georgios Karakonstantis, Dimitrios S. Nikolopoulos, Dimitris Gizopoulos, Pedro Trancoso, Yiannakis Sazeides, Christos D. Antonopoulos, Srikumar Venugopal, Shidhartha Das
2017	A	`conf`	Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017	—	`conf`	Hardware and software innovations in energy-efficient system-reliability monitoring. DFT Vasileios Tenentes, Charles Leech, Graeme M. Bragg, Geoff V. Merrett, Bashir M. Al-Hashimi, Hussam Amrouch, Jörg Henkel, Shidhartha Das
2017	A*	`conf`	Harnessing voltage margins for energy efficiency in multicore CPUs. MICRO George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das
2017	J	`jnl`	Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor. IEEE J. Solid State Circuits Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
2017	Misc	`conf`	Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper. CODES+ISSS Dave Burke, Dainius Jenkus, Issa Qiqieh, Rishad A. Shafik, Shidhartha Das, Alex Yakovlev
2016	—	`conf`	A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications. DSN Workshops Xabier Iturbe, Balaji Venu, Emre Ozer, Shidhartha Das
2016	J	`jnl`	Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. IET Comput. Digit. Tech. Robert C. Aitken, Vikas Chandra, Brian Cline, Shidhartha Das, David Pietromonaco, Lucian Shifren, Saurabh Sinha, Greg Yeric
2015	—	`conf`	14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster. ISSCC Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull
2015	—	`conf`	A 0.6V all-digital body-coupled wakeup transceiver for IoT applications. VLSIC Paul N. Whatmough, George Smart, Shidhartha Das, Yiannis Andreopoulos, David M. Bull
2015	A	`conf`	Analysis of adaptive clocking technique for resonant supply voltage noise mitigation. ISLPED Paul N. Whatmough, Shidhartha Das, David M. Bull
2015	A	`conf`	Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS. ISLPED Shidhartha Das, Paul N. Whatmough, David M. Bull
2014	J	`jnl`	A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull
2014	J	`jnl`	A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS. IEEE J. Solid State Circuits Paul N. Whatmough, Shidhartha Das, David M. Bull
2013	—	`conf`	A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation. CICC Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull
2013	—	`conf`	A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS. ISSCC Paul N. Whatmough, Shidhartha Das, David M. Bull
2013	J	`jnl`	Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms. IEEE Trans. Very Large Scale Integr. Syst. Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2012	—	`conf`	Selective time borrowing for DSP pipelines with hybrid voltage control loop. ASP-DAC Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2011	J	`jnl`	A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. IEEE J. Solid State Circuits David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
2011	J	`jnl`	Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". IEEE J. Solid State Circuits David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
2011	A*	`conf`	Error-resilient low-power DSP via path-delay shaping. DAC Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2010	—	`conf`	A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. ISSCC David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw
2010	C	`conf`	A robust FIR filter with in situ error detection. ISCAS Paul N. Whatmough, Izzat Darwazeh, David M. Bull, Shidhartha Das, Danny Kershaw
2009	C	`conf`	Adaptive Design for Nanometer Technology. ISCAS Shidhartha Das, David T. Blaauw
2009	A*	`conf`	Addressing design margins through error-tolerant circuits. DAC Shidhartha Das, David T. Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken
2009	—	`—`	Razor: A Variability-Tolerant Design Methodology for Low-Power and Robust Computing. Shidhartha Das
2009	J	`jnl`	RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE J. Solid State Circuits Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw
2008	A*	`conf`	DVFS in loop accelerators using BLADES. DAC Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull
2008	—	`conf`	Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance. ISSCC David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David M. Bull
2006	J	`jnl`	A self-tuning DVS processor using delay-error detection and correction. IEEE J. Solid State Circuits Shidhartha Das, David Roberts, SeokWoo Lee, Sanjay Pant, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
2004	A*	`conf`	Circuit-aware architectural simulation. DAC SeokWoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
2004	J	`jnl`	Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro Dan Ernst, Shidhartha Das, SeokWoo Lee, David T. Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner
2004	A	`conf`	Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED SeokWoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
2003	C	`conf`	Optimal Inductance for On-chip RLC Interconnections. ICCD Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester
2003	A*	`conf`	Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge