Shibaji Banerjee

12 papers Misc 3Journal 6Unranked 3
YearRankTypeTitle / Venue / Authors
2017 J jnl
An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization.
J. Low Power Electron.
Shibaji Banerjee, Jimson Mathew
2013 J jnl
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Comput. Electr. Eng.
Jimson Mathew, Saraju P. Mohanty, Shibaji Banerjee, Dhiraj K. Pradhan, Abusaleh M. Jabir
2011 J jnl
A Routing-Aware ILS Design Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty
2011 J jnl
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
J. Low Power Electron.
Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski
2011 Misc conf
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.
VLSI Design
Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski
2007 J jnl
An Efficient Scan Tree Design for Compact Test Pattern Set.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya
2006 Misc conf
An Efficient Scan Tree Design for Compact Test Pattern Set.
VLSI Design
Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya
2006 J jnl
An integrated DFT solution for mixed-signal SOCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shibaji Banerjee, Debdeep Mukhopadhyay, C. V. G. Rao, Dipanwita Roy Chowdhury
2006 — conf
Built-In Self-Test for Flash Memory Embedded in SoC.
DELTA
Shibaji Banerjee, Dipanwita Roy Chowdhury
2005 — conf
A programmable built-in self-test for embedded DRAMs.
MTDT
Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya
2005 Misc conf
Computer Aided Test (CAT) Tool for Mixed Signal SOCs.
VLSI Design
Shibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury
2005 — conf
CryptoScan: A Secured Scan Chain Architecture.
Asian Test Symposium
Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya