Shianling Wu

25 papers A 8C 1Misc 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2012 J jnl
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
ACM Trans. Design Autom. Electr. Syst.
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
2012 — conf
Physical-design-friendly hierarchical logic built-in self-test - A case study.
ISQED
Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang
2011 J jnl
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
2010 Misc conf
CSER: BISER-based concurrent soft-error resilience.
VTS
Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
2010 — conf
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.
DFT
Lizhen Yu, Jeffrey Hung, Boryau Sheu, Bill Huynh, Loc Nguyen, Shianling Wu, Laung-Terng Wang, Xiaoqing Wen
2010 — conf
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.
DFT
Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang
2010 J jnl
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone
2009 — conf
Analysis of Resistive Bridging Defects in a Synchronizer.
Asian Test Symposium
Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu
2009 — conf
Logic BIST Architecture for System-Level Test and Diagnosis.
Asian Test Symposium
Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, Feifei Zhao, Laung-Terng Wang
2009 J jnl
Turbo1500: Core-Based Design for Test and Diagnosis.
IEEE Des. Test Comput.
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008 — conf
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.
DFT
Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte
2008 — conf
Practical Challenges in Logic BIST Implementation.
ATS
Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami
2008 A conf
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
ITC
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008 J jnl
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Des. Test Comput.
Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu
2007 J jnl
At-Speed Logic BIST for IP Cores
CoRR
B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu
2006 A conf
A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.
ITC
Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu
2005 C conf
At-Speed Logic BIST Architecture for Multi-Clock Designs.
ICCD
Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo
2005 A conf
At-Speed Logic BIST for IP Cores.
DATE
B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu
2005 A conf
Test compression and logic BIST at your fingertips.
ITC
Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu
2005 A conf
UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.
ITC
Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang
2004 A conf
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
ITC
Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai
2000 — conf
Collaboration between Industry and Academia in Test Research.
Asian Test Symposium
Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
1998 A conf
A non-enumerative path delay fault simulator for sequential circuits.
ITC
Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
1996 — conf
Lessons Learned from Practical Applications of BIST/B-S Technology.
Asian Test Symposium
Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau
1985 A conf
A Sequential Circuit Test Generation System.
ITC
Sivanarayana Mallela, Shianling Wu