Shi-Yu Huang

158 papers A* 8A 18B 4C 4Misc 4Journal 66Unranked 54
YearRankTypeTitle / Venue / Authors
2026 J jnl
Falcon-H1R: Pushing the Reasoning Frontiers with a Hybrid Model for Efficient Test-Time Scaling.
CoRR
Falcon LLM Team, Iheb Chaabane, Puneesh Khanna, Suhail Mohmad, Slim Frikha, Shi-Yu Huang, Abdalgader Abubaker, Reda Alami, Mikhail Lubinets, Mohamed El Amine Seddik, Hakim Hacid
2025 — conf
A Scalable Authentication Scheme for Detecting Unauthorized Dice in A Multi-Die IC.
SMACD
Zheng-Hao Wang, Shi-Yu Huang, Chi-Kang Chen
2025 — conf
A Speed Learning Scheme To Mitigate The Silent Data Corruption in a Multi-Core Design.
ITC-Asia
Yun-Chieh Wang, Chun-Teng Chao, Shi-Yu Huang, Chi-Kang Chen
2025 J jnl
Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test.
IEEE Trans. Very Large Scale Integr. Syst.
Chen-Yu Huang, Shi-Yu Huang
2025 J jnl
Connectivity-Agnostic Built-In Self-Repair of Interconnects in a Chiplet IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chi Lai, Shi-Yu Huang
2024 J jnl
A Check-and-Balance Scheme in Multiphase Delay-Locked Loop.
IEEE Trans. Very Large Scale Integr. Syst.
Shu-Yu Chang, Shi-Yu Huang
2024 — conf
A Resilient All-Digital PLL Using Ping-Pong Delay Line.
ISOCC
Hsiang-Kai Teng, Shi-Yu Huang
2024 J jnl
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme.
J. Electron. Test.
Shun-Hua Yang, Shi-Yu Huang
2024 J jnl
Instant Test and Repair for TSVs using Differential Signaling.
J. Electron. Test.
Ching-Yi Wen, Shi-Yu Huang
2024 B conf
Keynote 2 - Sustainability and the Outlook of Semiconductor Industry.
ETS
Cheng-Wen Wu, Shi-Yu Huang
2024 J jnl
Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment.
IEEE Trans. Very Large Scale Integr. Syst.
Ko-Hong Lin, Ont-Derh Lin, Shi-Yu Huang, Duo Sheng
2024 A conf
Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test.
ITC
Chi Lai, Shi-Yu Huang
2024 — conf
Trojan Horse Detection for RISC-V Cores Using Cross-Auditing.
ATS
Wei-Po Huang, Shi-Yu Huang, Chi-Kang Chen, Siang-Cheng Huang
2023 J jnl
A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells.
IEEE Trans. Very Large Scale Integr. Syst.
Yung-Chuan Su, Shi-Yu Huang
2023 — conf
Cell-Based Aging Sensor Using Built-In Speed Grading.
NorCAS
Ont-Derh Lin, Shi-Yu Huang
2023 J jnl
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yung-Chuan Su, Shi-Yu Huang
2023 J jnl
Compiler of Reed-Solomon Codec for 400-Gb/s IEEE 802.3bs Standard.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lin Liu, Lai Chi, Shi-Yu Huang, Ka-Yi Yeh
2023 B conf
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs.
FPL
Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer
2023 J jnl
Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs.
CoRR
Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier M. Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu, Mark S. Neubauer
2023 — conf
Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL.
MWSCAS
Yi-Sheng Wang, Hsiang-Kai Teng, Shi-Yu Huang
2023 — conf
Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration.
ITC-Asia
Yi-Hsuan Lee, Wei-Hao Chen, Shi-Yu Huang
2023 — conf
Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test.
ITC-Asia
Chen-Lin Tsai, Shi-Yu Huang
2022 J jnl
Graph Neural Networks for Charged Particle Tracking on FPGAs.
Frontiers Big Data
Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte, Markus Atkinson, Gage DeZoort, Peter Elmer, Scott Hauck, Jin-Xuan Hu, Shih-Chieh Hsu, Bo-Cheng Lai, Mark S. Neubauer, Isobel Ojalvo, Savannah Thais, Matthew Trahms
2022 — conf
Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter.
ISOCC
Yung-Chuan Su, Shi-Yu Huang
2022 A conf
Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning.
ITC
Chen-Lin Tsai, Shi-Yu Huang
2022 J jnl
On-Chip Jitter Learning for PLL.
IEEE Des. Test
Wei-Hao Chen, Shi-Yu Huang
2022 J jnl
Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jun-Yu Yang, Shi-Yu Huang
2022 J jnl
Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jun-Yu Yang, Shi-Yu Huang
2021 — conf
A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal.
ITC-Asia
Chen-Lin Tsai, Wei-Hao Chen, Shi-Yu Huang
2021 J jnl
Graph Neural Networks for Charged Particle Tracking on FPGAs.
CoRR
Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M. Duarte, Markus Atkinson, Gage DeZoort, Peter Elmer, Jin-Xuan Hu, Shih-Chieh Hsu, Bo-Cheng Lai, Mark S. Neubauer, Isobel Ojalvo, Savannah Thais
2021 J jnl
Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor.
IEEE Trans. Emerg. Top. Comput.
Wei Chu, Shi-Yu Huang
2021 — conf
Rigorous Test Flow for PLL to Identify Weak Devices.
ITC-Asia
Yi-Hsuan Lee, Shi-Yu Huang
2020 — conf
A Voting Phase Detector Design with Mitigated Process Variation.
ISOCC
Derek Lin, Jun-Yu Yang, Shi-Yu Huang
2020 J jnl
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Tsai, Wu-Tung Cheng
2020 C conf
Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz.
ICCD
Wei Chu, Wei-Hao Chen, Shi-Yu Huang
2020 — conf
Fault and Soft Error Tolerant Delay-Locked Loop.
ATS
Jun-Yu Yang, Shi-Yu Huang
2020 — conf
Overview of On-Chip Performance Monitors for Clock Signals.
ATS
Shi-Yu Huang
2020 A conf
Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter.
ITC
Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang
2020 J jnl
Time-to-Digital Converter Compiler for On-Chip Instrumentation.
IEEE Des. Test
Chia-Hua Wu, Shi-Yu Huang, Yung-Fa Chou, Ding-Ming Kwai
2019 — conf
A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling.
NEWCAS
Wei Chu, Shi-Yu Huang
2019 J jnl
A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop.
IEEE Access
Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang
2019 J jnl
Cloud-Based Online Ageing Monitoring for IoT Devices.
IEEE Access
Guan-Hao Lian, Wei-Yi Chen, Shi-Yu Huang
2019 — conf
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.
ASP-DAC
Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng
2019 A conf
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia.
ITC
Kuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian
2019 — conf
Online Testing of Clock Delay Faults in a Clock Network.
ITC-Asia
Wei Chu, Shi-Yu Huang
2019 A conf
Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration.
ITC
Wei Chu, Shi-Yu Huang
2019 A* conf
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop.
DAC
Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang
2018 — conf
A Cell-Based Fractional-N Phase-Locked Loop Compiler.
SMACD
Cheng-En Lee, Shi-Yu Huang
2018 — conf
A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL.
ISOCC
Yu-Chi Wei, Shi-Yu Huang
2018 J jnl
Circuit and Methodology for Testing Small Delay Faults in the Clock Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shaofu Yang, Zhi-Yuan Wen, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2017 — conf
Cloud-Based PVT Monitoring System for IoT Devices.
ATS
Guan-Hao Lian, Shi-Yu Huang, Wei-Yi Chen
2017 C conf
DLL-Assisted Clock Synchronization Method for Multi-Die ICs.
ICCD
Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
2017 — conf
Resilient Cell-Based Architecture for Time-to-Digital Converter.
ISVLSI
Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai
2017 — conf
Test strategies for the clock and power distribution networks in a multi-die IC.
VLSI-DAT
Shi-Yu Huang
2016 — conf
A wide-range clock signal generation scheme for speed grading of a logic core.
HPCS
Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng
2016 — conf
Cell-based delay locked loop compiler.
ISOCC
Pei-Ching Huang, Shi-Yu Huang
2016 J jnl
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects.
IEEE Des. Test
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng
2016 — conf
Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs.
ATS
Shi-Yu Huang, Chih-Chieh Zheng
2016 A conf
Online slack-time binning for IO-registered die-to-die interconnects.
ITC
Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
2016 — conf
Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects.
ATS
Shi-Yu Huang
2016 B conf
Testing of small delay faults in a clock network.
ETS
Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2016 J jnl
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC.
IEEE Des. Test
Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng
2015 — conf
Cell-based programmable phase shifter design for pulsed radar SoC.
ASICON
Jinn-Yann Liu, Shi-Yu Huang, Ta-Shun Chu
2015 A conf
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.
DATE
Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng
2015 J jnl
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
2015 A conf
Monitoring the delay of long interconnects via distributed TDC.
ITC
Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2015 J jnl
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng
2015 — conf
Temperature-aware online testing of power-delivery TSVs.
3DIC
Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
2015 J jnl
The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems.
ACM Trans. Design Autom. Electr. Syst.
Cheng-Yen Lin, Chung-Wen Huang, Chi-Bang Kuan, Shi-Yu Huang, Jenq Kuen Lee
2014 — conf
On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs.
ATS
Shi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
2014 B conf
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs.
ETS
Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng
2014 J jnl
PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning.
IEEE Des. Test
Shi-Yu Huang, Li-Ren Huang
2014 J jnl
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration.
IEEE Trans. Very Large Scale Integr. Syst.
Chao-Wen Tzeng, Shi-Yu Huang, Pei-Ying Chao
2014 J jnl
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2014 J jnl
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
2013 J jnl
AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. Very Large Scale Integr. Syst.
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu
2013 C conf
At-speed BIST for interposer wires supporting on-the-spot diagnosis.
IOLTS
Shi-Yu Huang, Jeo-Yen Lee, Kun-Han Tsai, Wu-Tung Cheng
2013 J jnl
Cell-Based Process Resilient Multiphase Clock Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng
2013 A conf
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs.
ITC
Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
2013 J jnl
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou
2013 J jnl
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013 — conf
Mid-bond Interposer Wire Test.
Asian Test Symposium
Li-Ren Huang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
2013 J jnl
Oscillation-Based Prebond TSV Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Li-Ren Huang, Shi-Yu Huang, Stephen K. Sunter, Kun-Han Tsai, Wu-Tung Cheng
2013 J jnl
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2013 J jnl
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping.
IEEE Trans. Very Large Scale Integr. Syst.
Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang
2013 J jnl
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Yu-Hsiang Lin, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng
2013 — conf
Worst-case IR-drop monitoring with 1GHz sampling rate.
VLSI-DAT
Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
2012 — conf
A UWB IR timed-array radar using time-shifted direct-sampling architecture.
VLSIC
Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu
2012 A conf
A unified method for parametric fault characterization of post-bond TSVs.
ITC
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter
2012 — conf
Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.
VLSI-DAT
Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng, Shan-Chien Fang, Chia-Chien Weng
2012 J jnl
High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction.
IEEE Trans. Circuits Syst. Video Technol.
Feng-Cheng Huang, Shi-Yu Huang, Ji-Wei Ker, Yung-Chang Chen
2012 — conf
Programmable Leakage Test and Binning for TSVs.
Asian Test Symposium
Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2012 A* conf
Small delay testing for TSVs in 3-D ICs.
DAC
Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2011 J jnl
A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map.
J. Robotics
Bor-Woei Kuo, Hsun-Hao Chang, Yung-Chang Chen, Shi-Yu Huang
2011 J jnl
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Hsuan-Jung Hsu, Shi-Yu Huang
2011 A conf
A fully cell-based design for timing measurement of memory.
ITC
Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao
2011 A* conf
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
DAC
Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang
2011 A conf
Black-box leakage power modeling for cell library and SRAM compiler.
DATE
Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen
2011 J jnl
P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation.
IEEE J. Solid State Circuits
Cheng-Hung Lo, Shi-Yu Huang
2011 A* conf
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs.
DAC
Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh
2011 J jnl
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores.
IEEE Des. Test Comput.
Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu
2010 — conf
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
DFT
Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang
2010 — conf
PAC duo system power estimation at ESL.
ASP-DAC
Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang
2010 — conf
Performance Characterization of TSV in 3D IC via Sensitivity Analysis.
Asian Test Symposium
Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2010 Misc conf
Power aware SID-based simulator for embedded multicore DSP subsystems.
CODES+ISSS
Cheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee
2010 J jnl
Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao-Wen Tzeng, Shi-Yu Huang
2009 J jnl
Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang
2009 A conf
QC-Fill: An X-Fill method for quick-and-cool scan test.
DATE
Chao-Wen Tzeng, Shi-Yu Huang
2009 J jnl
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao-Wen Tzeng, Shi-Yu Huang
2009 J jnl
Resilient Self-V
IEEE J. Solid State Circuits
Ya-Chun Lai, Shi-Yu Huang, Hsuan-Jung Hsu
2009 J jnl
Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT).
IEEE J. Solid State Circuits
Ya-Chun Lai, Shi-Yu Huang
2008 J jnl
A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design.
IEEE Trans. Circuits Syst. II Express Briefs
Ya-Chun Lai, Shi-Yu Huang
2008 J jnl
A low-power SRAM for Viterbi decoder in wireless communication.
IEEE Trans. Consumer Electron.
Shin-Pao Cheng, Shi-Yu Huang
2008 J jnl
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.
ACM Trans. Design Autom. Electr. Syst.
Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang
2008 — conf
Two-Gear Low-Power Scan Test.
ATS
Chao-Wen Tzeng, Shi-Yu Huang
2008 J jnl
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.
IEEE Des. Test Comput.
Chao-Wen Tzeng, Shi-Yu Huang
2008 J jnl
X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs.
IEEE J. Solid State Circuits
Ya-Chun Lai, Shi-Yu Huang
2007 — conf
Built-In Speed Grading with a Process-Tolerant ADPLL.
ATS
Hsuan-Jung Hsu, Chun-Chieh Tu, Shi-Yu Huang
2007 J jnl
Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain.
IEEE Trans. Circuits Syst. II Express Briefs
Chao-Wen Tzeng, Shi-Yu Huang
2007 — conf
RT-level vector selection for realistic peak power simulation.
ACM Great Lakes Symposium on VLSI
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
2007 J jnl
Robust paradigm for diagnosing hold-time faults in scan chains.
IET Comput. Digit. Tech.
Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang
2006 A* conf
A network security processor design based on an integrated SOC design and test platform.
DAC
Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang
2006 J jnl
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults.
J. Electron. Test.
Yu-Chiun Lin, Shi-Yu Huang
2005 — conf
A low-power SRAM design using quiet-bitline architecture.
MTDT
Shin-Pao Cheng, Shi-Yu Huang
2005 J jnl
Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion.
IEEE Trans. Consumer Electron.
Ying-Chieh Chuang, Shih-Fang Chen, Shi-Yu Huang, Ya-Chin King
2005 — conf
Power estimation starategies for a low-power security processor.
ASP-DAC
Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang
2005 C conf
Quick Scan Chain Diagnosis Using Signal Profiling.
ICCD
Jheng-Syun Yang, Shi-Yu Huang
2004 — conf
A Fading Algorithm For Sequential Fault Diagnosis.
DFT
Shi-Yu Huang
2003 J jnl
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis.
J. Electron. Test.
Shi-Yu Huang
2003 — conf
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults.
Asian Test Symposium
Yu-Chiun Lin, Shi-Yu Huang
2003 — conf
Combinational circuit fault diagnosis using logic emulation.
ISCAS (5)
Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang
2003 A conf
Decomposition of Extended Finite State Machine for Low Power Design.
DATE
MingHung Lee, TingTing Hwang, Shi-Yu Huang
2003 J jnl
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.
J. Inf. Sci. Eng.
Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu
2002 — conf
Diagnosis Of Byzantine Open-Segment Faults.
Asian Test Symposium
Shi-Yu Huang
2002 — conf
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.
DFT
Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
2002 J jnl
Improving the Timing of Extended Finite State Machines Via Catalyst.
VLSI Design
Shi-Yu Huang
2002 Misc conf
Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation.
VTS
Shi-Yu Huang
2001 — conf
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.
Asian Test Symposium
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang
2001 Misc conf
On Improving the Accuracy Of Multiple Defect Diagnosis.
VTS
Shi-Yu Huang
2001 — conf
On speeding up extended finite state machines using catalyst circuitry.
ASP-DAC
Shi-Yu Huang
2001 — conf
Towards the logic defect diagnosis for partial-scan designs.
ASP-DAC
Shi-Yu Huang
2001 J jnl
Verifying sequential equivalence using ATPG techniques.
ACM Trans. Design Autom. Electr. Syst.
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
2000 J jnl
AQUILA: An Equivalence Checking System for Large Sequential Designs.
IEEE Trans. Computers
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
2000 — conf
High Performance/Delay Testing.
Asian Test Symposium
Shi-Yu Huang, Sudhakar M. Reddy
1999 J jnl
AutoFix: a hybrid tool for automatic logic rectification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
1999 J jnl
ErrorTracer: design error diagnosis based on fault simulation techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shi-Yu Huang, Kwang-Ting Cheng
1999 J jnl
Fault emulation: A new methodology for fault grading.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai
1998 — conf
A Hybrid Power Model for RTL Power Estimation.
ASP-DAC
Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho
1998 A* conf
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits.
DAC
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu
1997 — conf
AQUILA: An equivalence verifier for large sequential circuits.
ASP-DAC
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
1997 A conf
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis.
ITC
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng
1997 Misc conf
Incremental logic rectification.
VTS
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
1996 A conf
A novel methodology for transistor-level power estimation.
ISLPED
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
1996 A conf
An ATPG-Based Framework for Verifying Sequential Equivalence.
ITC
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser
1996 A* conf
Compact Vector Generation for Accurate Power Simulation.
DAC
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee
1996 A* conf
Error Correction Based on Verification Techniques.
DAC
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
1996 — conf
On Verifying the Correctness of Retimed Circuits.
Great Lakes Symposium on VLSI
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
1995 A conf
Fault emulation: a new approach to fault grading.
ICCAD
Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai