Sherief Reda - RankMe

190 papers A* 18A 36B 9C 9Misc 3Journal 71Unranked 36

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	RobuMTL: Enhancing Multi-Task Learning Robustness Against Weather Conditions. CoRR Tasneem Shaffee, Sherief Reda
2025	J	`jnl`	Approximate Logic Synthesis Using BLASYS. CoRR Jingxiao Ma, Soheil Hashemi, Sherief Reda
2025	A*	`conf`	FF-INT8: Efficient Forward-Forward DNN Training on Edge Devices with INT8 Precision. DAC Jingxiao Ma, Priyadarshini Panda, Sherief Reda
2025	J	`jnl`	FF-INT8: Efficient Forward-Forward DNN Training on Edge Devices with INT8 Precision. CoRR Jingxiao Ma, Priyadarshini Panda, Sherief Reda
2025	—	`conf`	Fast Chip Transient Temperature Simulation via Machine Learning. MLCAD Mohammadamin Hajikhodaverdian, Sherief Reda, Ayse K. Coskun
2025	A	`conf`	Fast Machine Learning Based Prediction for Temperature Simulation Using Compact Models. DATE Mohammadamin Hajikhodaverdian, Sherief Reda, Ayse K. Coskun
2025	J	`jnl`	HaShiFlex: A High-Throughput Hardened Shifter DNN Accelerator with Fine-Tuning Flexibility. CoRR Jonathan Herbst, Michael Pellauer, Sherief Reda
2025	—	`conf`	MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs. ASP-DAC Manar Abdelatty, Jingxiao Ma, Sherief Reda
2025	J	`jnl`	Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code. CoRR Manar Abdelatty, Maryam Nouh, Jacob K. Rosenstein, Sherief Reda
2024	J	`jnl`	Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in LLMs. CoRR Ahmed Agiza, Mohamed Mostagir, Sherief Reda
2024	J	`jnl`	Automatic MILP solver configuration by learning problem similarities. Ann. Oper. Res. Abdelrahman Hosny, Sherief Reda
2024	J	`jnl`	Electrical Capacitance Tomography of Cell Cultures on a CMOS Microelectrode Array. IEEE Trans. Biomed. Circuits Syst. Manar Abdelatty, Joseph Incandela, Kangping Hu, Pushkaraj S. Joshi, Joseph W. Larkin, Sherief Reda, Jacob K. Rosenstein
2024	—	`conf`	FairCIM: Fair Interference Mitigation by DNN Switching for Latency-Sensitive Inference Jobs. ACSOS Seyed Morteza Nabavinejad, Sherief Reda, Tian Guo
2024	J	`jnl`	HDLCopilot: Hardware Design Library Querying with Natural Language. CoRR Manar Abdelatty, Sherief Reda
2024	A*	`conf`	MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning. CVPR Ahmed Agiza, Marina Neseem, Sherief Reda
2024	J	`jnl`	MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning. CoRR Ahmed Agiza, Marina Neseem, Sherief Reda
2024	B	`conf`	MediatorDNN: Contention Mitigation for Co-Located DNN Inference Jobs. CLOUD Seyed Morteza Nabavinejad, Sherief Reda, Tian Guo
2024	J	`jnl`	MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs. CoRR Manar Abdelatty, Jingxiao Ma, Sherief Reda
2024	A*	`conf`	PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks. CVPR Marina Neseem, Conor McCullough, Randy Hsin, Chas Leichner, Shan Li, In Suk Chong, Andrew G. Howard, Lukasz Lew, Sherief Reda, Ville-Mikko Rautio, Daniele Moro
2024	J	`jnl`	PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks. CoRR Marina Neseem, Conor McCullough, Randy Hsin, Chas Leichner, Shan Li, In Suk Chong, Andrew G. Howard, Lukasz Lew, Sherief Reda, Ville-Mikko Rautio, Daniele Moro
2024	—	`conf`	PoliTune: Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in Large Language Models. AIES (1) Ahmed Agiza, Mohamed Mostagir, Sherief Reda
2024	J	`jnl`	torchmSAT: A GPU-Accelerated Approximation To The Maximum Satisfiability Problem. CoRR Abdelrahman Hosny, Sherief Reda
2023	—	`conf`	AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning. CVPR Workshops Marina Neseem, Ahmed Agiza, Sherief Reda
2023	J	`jnl`	AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning. CoRR Marina Neseem, Ahmed Agiza, Sherief Reda
2023	J	`jnl`	Automatic MILP Solver Configuration By Learning Problem Similarities. CoRR Abdelrahman Hosny, Sherief Reda
2023	A	`conf`	GraPhSyM: Graph Physical Synthesis Model. ICCAD Ahmed Agiza, Rajarshi Roy, Teodor-Dumitru Ene, Saad Godil, Sherief Reda, Bryan Catanzaro
2023	J	`jnl`	GraPhSyM: Graph Physical Synthesis Model. CoRR Ahmed Agiza, Rajarshi Roy, Teodor-Dumitru Ene, Saad Godil, Sherief Reda, Bryan Catanzaro
2023	—	`conf`	Microscale 3-D Capacitance Tomography with a CMOS Sensor Array. BioCAS Manar Abdelatty, Joseph Incandela, Kangping Hu, Joseph W. Larkin, Sherief Reda, Jacob K. Rosenstein
2023	J	`jnl`	Microscale 3-D Capacitance Tomography with a CMOS Sensor Array. CoRR Manar Abdelatty, Joseph Incandela, Kangping Hu, Joseph W. Larkin, Sherief Reda, Jacob K. Rosenstein
2023	—	`conf`	RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability. ASP-DAC Jingxiao Ma, Sherief Reda
2023	J	`jnl`	Throughput Maximization of DNN Inference: Batching or Multi-Tenancy? CoRR Seyed Morteza Nabavinejad, Masoumeh Ebrahimi, Sherief Reda
2023	A	`conf`	WeNet: Configurable Neural Network with Dynamic Weight-Enabling for Efficient Inference. ISLPED Jingxiao Ma, Sherief Reda
2022	B	`conf`	ARBench: Augmented Reality Benchmark For Mobile Devices. ISPASS Sofiane Chetoui, Rahul Shahi, Seif Abdelaziz, Abhinav Golas, Farrukh Hijaz, Sherief Reda
2022	B	`conf`	Alternating Blind Identification of Power Sources for Mobile SoCs. ICPE Sofiane Chetoui, Michael Chen, Abhinav Golas, Farrukh Hijaz, Adel Belouchrani, Sherief Reda
2022	J	`jnl`	Approximate Logic Synthesis Using Boolean Matrix Factorization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jingxiao Ma, Soheil Hashemi, Sherief Reda
2022	J	`jnl`	CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices. IEEE Embed. Syst. Lett. Sofiane Chetoui, Sherief Reda
2022	J	`jnl`	Characterizing and Optimizing EDA Flows for the Cloud. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abdelrahman Hosny, Sherief Reda
2022	J	`jnl`	Coordinated Batching and DVFS for DNN Inference on GPU Accelerators. IEEE Trans. Parallel Distributed Syst. Seyed Morteza Nabavinejad, Sherief Reda, Masoumeh Ebrahimi
2022	J	`jnl`	ISLPED 2021: The 25th Anniversary! IEEE Des. Test Yiran Chen, Sherief Reda
2022	J	`jnl`	PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zihao Yuan, Prachi Shukla, Sofiane Chetoui, Sean S. Nemtzow, Sherief Reda, Ayse K. Coskun
2022	J	`jnl`	RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability. CoRR Jingxiao Ma, Sherief Reda
2021	A	`conf`	AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices. ICCAD Marina Neseem, Sherief Reda
2021	J	`jnl`	AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices. CoRR Marina Neseem, Sherief Reda
2021	—	`conf`	BatchSizer: Power-Performance Trade-off for DNN Inference. ASP-DAC Seyed Morteza Nabavinejad, Sherief Reda, Masoumeh Ebrahimi
2021	J	`jnl`	BayesTuner: Leveraging Bayesian Optimization For DNN Inference Configuration Selection. IEEE Comput. Archit. Lett. Seyed Morteza Nabavinejad, Sherief Reda
2021	J	`jnl`	BitTrain: Sparse Bitmap Compression for Memory-Efficient Training on the Edge. CoRR Abdelrahman Hosny, Marina Neseem, Sherief Reda
2021	A	`conf`	Characterizing and Optimizing EDA Flows for the Cloud. DATE Abdelrahman Hosny, Sherief Reda
2021	J	`jnl`	Characterizing and Optimizing EDA Flows for the Cloud. CoRR Abdelrahman Hosny, Sherief Reda
2021	J	`jnl`	Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. IEEE Des. Test Sherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon
2021	Misc	`conf`	Sparse Bitmap Compression for Memory-Efficient Training on the Edge. SEC Abdelrahman Hosny, Marina Neseem, Sherief Reda
2021	A	`conf`	Workload- and User-aware Battery Lifetime Management for Mobile SoCs. DATE Sofiane Chetoui, Sherief Reda
2020	A	`conf`	A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies. DATE Zihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Zhengmao Lu, Evelyn Wang, Sherief Reda, Ayse K. Coskun
2020	J	`jnl`	A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks. ACM J. Emerg. Technol. Comput. Syst. Hokchhay Tann, Heng Zhao, Sherief Reda
2020	A*	`conf`	AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices. DAC Marina Neseem, Jon Nelson, Sherief Reda
2020	J	`jnl`	AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices. CoRR Marina Neseem, Jon Nelson, Sherief Reda
2020	B	`conf`	ApproxDNN: Incentivizing DNN Approximation in Cloud. CCGRID Seyed Morteza Nabavinejad, Lena Mashayekhy, Sherief Reda
2020	J	`jnl`	Approximate Logic Synthesis: A Survey. Proc. IEEE Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda
2020	J	`jnl`	Coordinated Self-Tuning Thermal Management Controller for Mobile Devices. IEEE Des. Test Sofiane Chetoui, Sherief Reda
2020	—	`conf`	DRiLLS: Deep Reinforcement Learning for Logic Synthesis. ASP-DAC Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda
2020	J	`jnl`	Dual-precision fixed-point arithmetic for low-power ray-triangle intersections. Comput. Graph. Krishna Rajan, Soheil Hashemi, Ulya R. Karpuzcu, Michael C. Doggett, Sherief Reda
2020	A	`ed.`	ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, Massachusetts, August 10-12, 2020 ISLPED David Atienza Alonso, Qinru Qiu, Sherief Reda, Yiran Chen
2020	J	`jnl`	LoCool: Fighting Hot Spots Locally for Improving System Energy Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fulya Kaplan, Mostafa Said, Sherief Reda, Ayse K. Coskun
2020	—	`conf`	Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring. VLSI-SoC (Selected Papers) Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein
2020	—	`conf`	Overview of the OpenROAD Digital Design Flow from RTL to GDS. VLSI-DAT Sherief Reda
2020	J	`jnl`	PowerCoord: Power capping coordination for multi-CPU/GPU servers using reinforcement learning. Sustain. Comput. Informatics Syst. Reza Azimi, Chao Jing, Sherief Reda
2020	C	`conf`	Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity. VLSI-SOC Xiaoyu Lian, Sherief Reda, Jacob K. Rosenstein
2020	C	`conf`	Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators. VLSI-SOC Shanshan Dai, Caleb R. Tulloss, Xiaoyu Lian, Kangping Hu, Sherief Reda, Jacob K. Rosenstein
2019	J	`jnl`	A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks. CoRR Hokchhay Tann, Heng Zhao, Sherief Reda
2019	—	`book`	Approximate Circuits, Methodologies and CAD. Approximate Circuits Sherief Reda, Muhammad Shafique
2019	—	`ch.`	Approximate Computing for Iris Recognition Systems. Approximate Circuits Hokchhay Tann, Soheil Hashemi, Francesco Buttafuoco, Sherief Reda
2019	—	`ch.`	Approximate Logic Synthesis Using Boolean Matrix Factorization. Approximate Circuits Soheil Hashemi, Hokchhay Tann, Sherief Reda
2019	—	`ch.`	Approximate Multipliers and Dividers Using Dynamic Bit Selection. Approximate Circuits Soheil Hashemi, Sherief Reda
2019	J	`jnl`	Automated High-Level Generation of Low-Power Approximate Computing Circuits. IEEE Trans. Emerg. Top. Comput. Kumud Nepal, Soheil Hashemi, Hokchhay Tann, R. Iris Bahar, Sherief Reda
2019	J	`jnl`	Coordinated DVFS and Precision Control for Deep Neural Networks. IEEE Comput. Archit. Lett. Seyed Morteza Nabavinejad, Hassan Hafez-Kolahi, Sherief Reda
2019	J	`jnl`	DRiLLS: Deep Reinforcement Learning for Logic Synthesis. CoRR Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda
2019	A	`conf`	Generalized Matrix Factorization Techniques for Approximate Logic Synthesis. DATE Soheil Hashemi, Sherief Reda
2019	—	`ch.`	Lightweight Deep Neural Network Accelerators Using Approximate SW/HW Techniques. Approximate Circuits Hokchhay Tann, Soheil Hashemi, Sherief Reda
2019	A	`conf`	Modeling and Optimization of Chip Cooling with Two-Phase Vapor Chambers. ISLPED Zihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Sherief Reda, Evelyn Wang, Ayse K. Coskun
2019	J	`jnl`	Principles of Information Storage in Small-Molecule Mixtures. CoRR Jacob K. Rosenstein, Christopher Rose, Sherief Reda, Peter M. Weber, Eunsuk Kim, Jason Sello, Joseph Geiser, Eamonn Kennedy, Christopher E. Arcadia, Amanda Dombroski, Kady Oakley, Shui Ling Chen, Hokchhay Tann, Brenda M. Rubenstein
2019	A*	`conf`	Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu
2018	A	`conf`	Approximate computing for biometrie security systems: A case study on iris scanning. DATE Soheil Hashemi, Hokchhay Tann, Francesco Buttafuoco, Sherief Reda
2018	J	`jnl`	BLASYS: Approximate Logic Synthesis Using Boolean Matrix Factorization. CoRR Soheil Hashemi, Hokchhay Tann, Sherief Reda
2018	A*	`conf`	BLASYS: approximate logic synthesis using boolean matrix factorization. DAC Soheil Hashemi, Hokchhay Tann, Sherief Reda
2018	B	`conf`	Computing with Chemicals: Perceptrons Using Mixtures of Small Molecules. ISIT Christopher Rose, Sherief Reda, Brenda M. Rubenstein, Jacob K. Rosenstein
2018	J	`jnl`	Flexible Deep Neural Network Processing. CoRR Hokchhay Tann, Soheil Hashemi, Sherief Reda
2018	J	`jnl`	Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques. CoRR Kapil Dev, Indrani Paul, Wei Huang, Yasuko Eckert, Wayne P. Burleson, Sherief Reda
2018	—	`conf`	Parallelized Linear Classification with Volumetric Chemical Perceptrons. ICRC Christopher E. Arcadia, Hokchhay Tann, Amanda Dombroski, Kady Ferguson, Shui Ling Chen, Eunsuk Kim, Christopher Rose, Brenda M. Rubenstein, Sherief Reda, Jacob K. Rosenstein
2018	J	`jnl`	Parallelized Linear Classification with Volumetric Chemical Perceptrons. CoRR Christopher E. Arcadia, Hokchhay Tann, Amanda Dombroski, Kady Ferguson, Shui Ling Chen, Eunsuk Kim, Christopher Rose, Brenda M. Rubenstein, Sherief Reda, Jacob K. Rosenstein
2018	—	`conf`	PowerCoord: A Coordinated Power Capping Controller for Multi-CPU/GPU Servers. IGSC Reza Azimi, Chao Jing, Sherief Reda
2018	A	`conf`	QoR-aware power capping for approximate big data processing. DATE Seyed Morteza Nabavinejad, Xin Zhan, Reza Azimi, Maziar Goudarzi, Sherief Reda
2018	J	`jnl`	Scale-Out vs Scale-Up: A Study of ARM-based SoCs on Server-Class Workloads. ACM Trans. Model. Perform. Evaluation Comput. Syst. Reza Azimi, Tyler Fox, Wendy Gonzalez, Sherief Reda
2018	—	`conf`	Understanding the Sources of Power Consumption in Mobile SoCs. IGSC Mostafa Said, Sofiane Chetoui, Adel Belouchrani, Sherief Reda
2017	A	`conf`	Blind identification of power sources in processors. DATE Sherief Reda, Adel Belouchrani
2017	J	`jnl`	CARB: A C-State Power Management Arbiter for Latency-Critical Workloads. IEEE Comput. Archit. Lett. Xin Zhan, Reza Azimi, Svilen Kanev, David M. Brooks, Sherief Reda
2017	—	`conf`	CloudV: A cloud-based educational digital design environment. MSE Mohamed Shalan, Sherief Reda
2017	A*	`conf`	Fast Decentralized Power Capping for Server Clusters. HPCA Reza Azimi, Masoud Badiei, Xin Zhan, Na Li, Sherief Reda
2017	A*	`conf`	Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. DAC Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
2017	J	`jnl`	Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. CoRR Hokchhay Tann, Soheil Hashemi, Iris Bahar, Sherief Reda
2017	C	`conf`	LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs. ICCD Samuel Steffl, Sherief Reda
2017	J	`jnl`	Scheduling on CPU + GPU Processors Under Dynamic Conditions. J. Low Power Electron. Kapil Dev, Xin Zhan, Sherief Reda
2017	C	`conf`	Understanding the Role of GPGPU-Accelerated SoC-Based ARM Clusters. CLUSTER Reza Azimi, Tyler Fox, Sherief Reda
2017	A	`conf`	Understanding the impact of precision quantization on the accuracy and energy of neural networks. DATE Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda
2016	A*	`conf`	A low-power dynamic divider for approximate applications. DAC Soheil Hashemi, R. Iris Bahar, Sherief Reda
2016	B	`conf`	Creating Soft Heterogeneity in Clusters Through Firmware Re-configuration. CCGrid Xin Zhan, Mohammed Shoaib, Sherief Reda
2016	B	`conf`	DiBA: Distributed Power Budget Allocation for Large-Scale Computing Clusters. CCGrid Masoud Badiei, Xin Zhan, Reza Azimi, Sherief Reda, Na Li
2016	B	`conf`	Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. FPL Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar
2016	—	`conf`	Power-aware characterization and mapping of workloads on CPU-GPU processors. IISWC Kapil Dev, Xin Zhan, Sherief Reda
2016	J	`jnl`	Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off. CoRR Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
2016	Misc	`conf`	Runtime configurable deep neural networks for energy-accuracy trade-off. CODES+ISSS Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
2016	—	`conf`	Scheduling Challenges and Opportunities in Integrated CPU+GPU Processors. ESTIMedia Kapil Dev, Sherief Reda
2016	J	`jnl`	Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks. CoRR Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda
2016	—	`conf`	Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs. ISVLSI Kapil Dev, Sherief Reda, Indrani Paul, Wei Huang, Wayne P. Burleson
2015	A	`conf`	DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. ICCAD Soheil Hashemi, R. Iris Bahar, Sherief Reda
2015	—	`conf`	How Good Are Low-Power 64-Bit SoCs for Server-Class Workloads? IISWC Reza Azimi, Xin Zhan, Sherief Reda
2015	A	`conf`	Making sense of thermoelectrics for processor thermal management and energy harvesting. ISLPED Sriram Jayakumar, Sherief Reda
2015	J	`jnl`	Power Budgeting Techniques for Data Centers. IEEE Trans. Computers Xin Zhan, Sherief Reda
2014	A	`conf`	ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. DATE Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda
2014	J	`jnl`	Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. ACM Trans. Reconfigurable Technol. Syst. Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda
2014	J	`jnl`	Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abdullah Nazma Nowroz, Kangqiao Hu, Farinaz Koushanfar, Sherief Reda
2014	A	`conf`	Thermal-aware layout planning for heterogeneous datacenters. ISLPED Reza Azimi, Xin Zhan, Sherief Reda
2013	A	`conf`	High-sensitivity hardware trojan detection using multimodal characterization. DATE Kangqiao Hu, Abdullah Nazma Nowroz, Sherief Reda, Farinaz Koushanfar
2013	A*	`conf`	High-throughput TSV testing and characterization for 3D integration using thermal mapping. DAC Kapil Dev, Gary L. Woods, Sherief Reda
2013	A	`conf`	Mitigating dark-silicon problems using superlattice-based thermoelectric coolers. DATE Francesco Paterna, Sherief Reda
2013	J	`jnl`	Post-silicon power mapping techniques for integrated circuits. Integr. Sherief Reda, Abdullah Nazma Nowroz, Ryan Cochran, Stefan Angelevski
2013	J	`jnl`	Power Mapping of Integrated Circuits Using AC-Based Thermography. IEEE Trans. Very Large Scale Integr. Syst. Abdullah Nazma Nowroz, Gary L. Woods, Sherief Reda
2013	A	`conf`	Power mapping and modeling of multi-core processors. ISLPED Kapil Dev, Abdullah Nazma Nowroz, Sherief Reda
2013	A*	`conf`	Techniques for energy-efficient power budgeting in data centers. DAC Xin Zhan, Sherief Reda
2013	A	`conf`	vCap: Adaptive power capping for virtualized servers. ISLPED Can Hankendi, Sherief Reda, Ayse K. Coskun
2012	J	`jnl`	Adaptive Power Capping for Servers with Multithreaded Workloads. IEEE Micro Sherief Reda, Ryan Cochran, Ayse K. Coskun
2012	Misc	`conf`	Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. FCCM Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda
2012	J	`jnl`	Power Modeling and Characterization of Computing Devices: A Survey. Found. Trends Electron. Des. Autom. Sherief Reda, Abdullah Nazma Nowroz
2012	—	`conf`	Temperature-aware computing: Achievements and remaining challenges. IGCC Dhireesha Kudithipudi, Ayse K. Coskun, Sherief Reda, Qinru Qiu
2012	J	`jnl`	Thermal prediction and adaptive control through workload phase detection. ACM Trans. Design Autom. Electr. Syst. Ryan Cochran, Sherief Reda
2011	A	`conf`	Identifying the optimal energy-efficient operating points of parallel workloads. ICCAD Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda
2011	J	`jnl`	Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques. IEEE Trans. Computers Sherief Reda, Ryan Cochran, Abdullah Nazma Nowroz
2011	A*	`conf`	Improved post-silicon power modeling using AC lock-in techniques. DAC Abdullah Nazma Nowroz, Gary L. Woods, Sherief Reda
2011	A*	`conf`	Pack & Cap: adaptive DVFS and thread packing under power caps. MICRO Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda
2011	J	`jnl`	Thermal and Power Characterization of Real Computing Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. Sherief Reda
2011	A	`conf`	Thermal and power characterization of field-programmable gate arrays. FPGA Abdullah Nazma Nowroz, Sherief Reda
2010	A*	`conf`	Consistent runtime thermal prediction and control through workload phase detection. DAC Ryan Cochran, Sherief Reda
2010	—	`conf`	Early estimation of TSV area for power delivery in 3-D integrated circuits. 3DIC Nauman H. Khan, Sherief Reda, Soha Hassoun
2010	—	`conf`	Fast, accurate a priori routing delay estimation. SLIP Jinhai Qiu, Sherief Reda, Soha Hassoun
2010	—	`ed.`	International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010 SLIP Sherief Reda, Janet Meiling Wang
2010	A	`conf`	Post-silicon power characterization using thermal infrared emissions. ISLPED Ryan Cochran, Abdullah Nazma Nowroz, Sherief Reda
2010	A*	`conf`	Thermal monitoring of real processors: techniques for sensor allocation and full characterization. DAC Abdullah Nazma Nowroz, Ryan Cochran, Sherief Reda
2009	A	`conf`	Analyzing the impact of process variations on parametric measurements: Novel models and applications. DATE Sherief Reda, Sani R. Nassif
2009	—	`conf`	Central vs. distributed dynamic thermal management for multi-core processors: which one is better? ACM Great Lakes Symposium on VLSI Michael Kadin, Sherief Reda, Augustus K. Uht
2009	A	`conf`	High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA Roto Le, Sherief Reda, R. Iris Bahar
2009	—	`conf`	High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI Roto Le, Sherief Reda, R. Iris Bahar
2009	J	`jnl`	Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. Sherief Reda, Gregory Smith, Larry Smith
2009	A	`conf`	Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED Sherief Reda, Aung Si, R. Iris Bahar
2009	A*	`conf`	Spectral techniques for high-resolution thermal characterization with limited sensor data. DAC Ryan Cochran, Sherief Reda
2009	—	`ed.`	The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings SLIP Chung-Kuan Cheng, Sherief Reda
2009	—	`conf`	Using circuit structural analysis techniques for networks in systems biology. SLIP Sherief Reda
2008	C	`conf`	Frequency and voltage planning for multi-core processors under thermal constraints. ICCD Michael Kadin, Sherief Reda
2008	A	`conf`	Frequency planning for multi-core processors under thermal constraints. ISLPED Michael Kadin, Sherief Reda
2008	J	`jnl`	Parametric yield management for 3D ICs: Models and strategies for improvement. ACM J. Emerg. Technol. Comput. Syst. Cesare Ferri, Sherief Reda, R. Iris Bahar
2008	—	`conf`	Within-die process variations: How accurately can they be statistically modeled? ASP-DAC Brendan Hargreaves, Henrik Hult, Sherief Reda
2007	—	`ch.`	APlace: A High Quality, Large-Scale Analytical Placer. Modern Circuit Placement Andrew B. Kahng, Sherief Reda, Qinke Wang
2007	C	`conf`	Hardware libraries: An architecture for economic acceleration in soft multi-core environments. ICCD David Meisner, Sherief Reda
2007	—	`conf`	On-Line Adjustable Buffering for Runtime Power Reduction. ISQED Andrew B. Kahng, Sherief Reda, Puneet Sharma
2007	A	`conf`	Strategies for improving the parametric yield and profits of 3D ICs. ICCAD Cesare Ferri, Sherief Reda, R. Iris Bahar
2006	J	`jnl`	A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
2006	—	`conf`	A tale of two nets: studies of wirelength progression in physical design. SLIP Andrew B. Kahng, Sherief Reda
2006	J	`jnl`	Computer-Aided Optimization of DNA Array Design and Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
2006	—	`conf`	Effective linear programming based placement methods. ISPD Sherief Reda, Amit Chowdhary
2006	J	`jnl`	New and improved BIST diagnosis methods from combinatorial Group testing theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sherief Reda
2006	J	`jnl`	Wirelength minimization for min-cut placements via placement feedback. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sherief Reda
2006	J	`jnl`	Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Sherief Reda
2005	—	`conf`	A semi-persistent clustering technique for VLSI circuit placement. ISPD Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
2005	—	`conf`	APlace: a general analytic placement framework. ISPD Andrew B. Kahng, Sherief Reda, Qinke Wang
2005	A	`conf`	Architecture and details of a high quality, large-scale analytical placer. ICCAD Andrew B. Kahng, Sherief Reda, Qinke Wang
2005	—	`conf`	Evaluation of placer suboptimality via zero-change netlist transformations. ISPD Andrew B. Kahng, Sherief Reda
2005	A	`conf`	Intrinsic shortest path length: a new, accurate a priori wirelength estimator. ICCAD Andrew B. Kahng, Sherief Reda
2005	A*	`conf`	Power-aware placement. DAC Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang
2004	A	`conf`	Boosting: Min-Cut Placement with Improved Signal Delay. DATE Andrew B. Kahng, Igor L. Markov, Sherief Reda
2004	—	`conf`	Combinatorial group testing methods for the BIST diagnosis problem. ASP-DAC Andrew B. Kahng, Sherief Reda
2004	J	`jnl`	Match twice and stitch: a new TSP tour construction heuristic. Oper. Res. Lett. Andrew B. Kahng, Sherief Reda
2004	—	`conf`	On legalization of row-based placements. ACM Great Lakes Symposium on VLSI Andrew B. Kahng, Igor L. Markov, Sherief Reda
2004	A*	`conf`	Placement feedback: a concept and method for better min-cut placements. DAC Andrew B. Kahng, Sherief Reda
2004	J	`jnl`	Scalable Heuristics for Design of DNA Probe Arrays. J. Comput. Biol. Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
2003	C	`conf`	Design Flow Enhancements for DNA Arrays. ICCD Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
2003	B	`conf`	Engineering a scalable placement heuristic for DNA probe arrays. RECOMB Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
2003	A	`conf`	Evaluation of Placement Techniques for DNA Probe Array Layout. ICCAD Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
2002	C	`conf`	Border Length Minimization in DNA Array Design. WABI Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky
2002	—	`conf`	On the Relation between SAT and BDDs for Equivalence Checking. ISQED Sherief Reda, Rolf Drechsler, Alex Orailoglu
2002	A	`conf`	Reducing Test Application Time Through Test Data Mutation Encoding. DATE Sherief Reda, Alex Orailoglu
2001	A	`conf`	Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. DATE Sherief Reda, Ashraf Salem
2001	—	`conf`	On the use of don't cares during symbolic reachability analysis. ISCAS (5) Sherief Reda, Ayman Wahba, Ashraf Salem, Dominique Borrione, M. Ghonaimy
2000	C	`conf`	M-CHECK: a multiple engine combinational equivalence checker. ISCAS Sherief Reda, Ayman Wahba, Ashraf Salem