Sheqin Dong - RankMe

111 papers A* 2A 2C 10Journal 33Unranked 64

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array. ACM Trans. Design Autom. Electr. Syst. Zhenyi Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu
2024	—	`conf`	MORE-Router+: Multilayer Multi-capacity ORdered Escape Routing via Bus-oriented Layer Assignment. ISQED Zhenyi Gao, Sheqin Dong, Zifei Cheng, Wenjian Yu
2023	—	`conf`	MC-MCF: A Multi-Capacity Model for Ordered Escape Routing. ISQED Zhenyi Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu
2020	—	`conf`	A Constraint-Driven Compact Model with Partition Strategy for Ordered Escape Routing. ACM Great Lakes Symposium on VLSI Zhaopo Liao, Sheqin Dong
2018	—	`conf`	A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm. ISVLSI Qian Chen, Sheqin Dong
2018	J	`jnl`	Ordered Escape Routing with Consideration of Differential Pair and Blockage. ACM Trans. Design Autom. Electr. Syst. Fengxian Jiao, Sheqin Dong
2018	C	`conf`	Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. ISCAS Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann
2017	J	`jnl`	TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kan Wang, Sheqin Dong, Fengxian Jiao
2016	—	`conf`	Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow. ASP-DAC Fengxian Jiao, Sheqin Dong
2015	J	`jnl`	Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sheqin Dong, Jianchang Ao, Fuqi Luo
2014	J	`jnl`	Floorplanning and Topology Generation for Application-Specific Network-on-Chip. CoRR Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2014	J	`jnl`	Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kan Wang, Sheqin Dong, Huaxi Wang, Qian Chen, Tao Lin
2014	J	`jnl`	Multi-Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR Bei Yu, Sheqin Dong, Satoshi Goto
2014	J	`jnl`	Network flow-based simultaneous retiming and slack budgeting for low power design. CoRR Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2014	C	`conf`	Post-floorplanning power optimization for MSV-driven application specific NoC design. ISCAS Kan Wang, Sheqin Dong
2014	J	`jnl`	Voltage and Level-Shifter Assignment Driven Floorplanning. CoRR Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2013	—	`conf`	Delay-driven layer assignment in global routing under multi-tier interconnect structure. ISPD Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto
2013	—	`conf`	Escape routing of mixed-pattern signals based on staggered-pin-array PCBs. ISPD Kan Wang, Huaxi Wang, Sheqin Dong
2013	J	`jnl`	Multi-bend bus-driven floorplanning considering fixed-outline constraints. Integr. Wenxu Sheng, Sheqin Dong
2013	—	`conf`	Power optimization for application-specific 3D network-on-chip with multiple supply voltages. ASP-DAC Kan Wang, Sheqin Dong
2012	J	`jnl`	Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. IEICE Trans. Electron. Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto
2012	—	`conf`	Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. ISQED Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong
2012	—	`conf`	Linear optimal one-sided single-detour algorithm for untangling twisted bus. ASP-DAC Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto
2012	J	`jnl`	Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen, Satoshi Goto
2012	J	`jnl`	UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Trans. Very Large Scale Integr. Syst. Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan
2012	—	`conf`	Voltage island-driven power optimization for application specific network-on-chip design. ACM Great Lakes Symposium on VLSI Kan Wang, Sheqin Dong, Satoshi Goto
2011	—	`conf`	Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. ISQED Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto
2011	J	`jnl`	Buffer Planning for IP Placement Using Sliced-LFF. VLSI Design Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto
2011	J	`jnl`	Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong
2011	—	`conf`	Network flow-based simultaneous retiming and slack budgeting for low power design. ASP-DAC Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2011	—	`conf`	Novel and efficient min cut based voltage assignment in gate level. ISQED Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto
2011	—	`conf`	Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong
2011	—	`conf`	Through-Silicon-Via assignment for 3D ICs. ASICON Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto
2010	—	`conf`	A revisit to voltage partitioning problem. ACM Great Lakes Symposium on VLSI Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto
2010	—	`conf`	Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
2010	—	`conf`	Fixed outline multi-bend bus driven floorplanning. ISQED Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto
2010	—	`conf`	Floorplanning and topology generation for application-specific network-on-chip. ASP-DAC Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2010	J	`jnl`	Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. Integr. Xu He, Sheqin Dong, Yuchun Ma
2010	—	`conf`	Wirelength-driven force-directed 3D FPGA placement. ACM Great Lakes Symposium on VLSI Wentao Sui, Sheqin Dong, Jinian Bian
2009	C	`conf`	Buffer Planning for 3D ICs. ISCAS Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto
2009	—	`conf`	Integrated interlayer via planning and pin assignment for 3D ICs. SLIP Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto
2009	J	`jnl`	Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2009	—	`conf`	Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
2009	J	`jnl`	Voltage and Level-Shifter Assignment Driven Floorplanning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2009	—	`conf`	Voltage-island driven floorplanning considering level-shifter positions. ACM Great Lakes Symposium on VLSI Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen
2008	A	`conf`	A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng
2008	—	`conf`	Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	C	`conf`	Cache miss reduction through hardware-assisted loop optimization. CSCWD Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto
2008	J	`jnl`	Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	J	`jnl`	Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	—	`conf`	HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto
2008	—	`conf`	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong
2008	—	`conf`	Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto
2007	C	`conf`	A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma
2007	C	`conf`	A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD Kang Zhao, Jinian Bian, Sheqin Dong
2007	J	`jnl`	APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. Yaoguang Wei, Sheqin Dong, Xianlong Hong
2007	—	`conf`	An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma
2007	—	`conf`	An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
2007	—	`conf`	Congestion Driven Buffer Planning for X-Architecture. ISQED Hongjie Bai, Sheqin Dong, Xianlong Hong
2007	—	`conf`	Interconnect Power Optimization Based on Timing Analysis. ISVLSI Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong
2007	—	`conf`	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou
2007	—	`conf`	Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong
2006	—	`conf`	A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS Kang Zhao, Jinian Bian, Sheqin Dong
2006	—	`conf`	A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
2006	—	`conf`	A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma
2006	C	`conf`	Buffer planning based on block exchanging. ISCAS Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
2006	—	`conf`	Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong
2006	C	`conf`	Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS Sheqin Dong, Shuyi Zheng, Xianlong Hong
2006	J	`jnl`	General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2006	C	`conf`	On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu
2006	—	`conf`	Signal-path driven partition and placement for analog circuit. ASP-DAC Di Long, Xianlong Hong, Sheqin Dong
2006	—	`conf`	Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong
2006	J	`jnl`	VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng
2005	C	`conf`	A New Buffer Planning Algorithm Based on Room Resizing. EUC Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
2005	—	`conf`	A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani
2005	—	`conf`	An efficient algorithm to fixed-outline floorplanning based on instance augmentation. CAD/Graphics Rong Liu, Sheqin Dong, Xianlong Hong
2005	—	`conf`	An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC Renshen Wang, Sheqin Dong, Xianlong Hong
2005	—	`conf`	Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005	J	`jnl`	Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
2005	—	`conf`	Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI Rong Liu, Sheqin Dong, Xianlong Hong
2005	—	`conf`	Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani
2005	—	`conf`	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2005	—	`conf`	LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu
2005	—	`conf`	Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) Di Long, Xianlong Hong, Sheqin Dong
2005	—	`conf`	Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005	—	`conf`	VLSI block placement with alignment constraints based on corner block list. ISCAS (6) Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2004	J	`jnl`	A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	A buffer planning algorithm with congestion optimization. ASP-DAC Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	Buffer allocation algorithm with consideration of routing congestion. ASP-DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	J	`jnl`	Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	J	`jnl`	Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004	J	`jnl`	Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
2004	—	`conf`	Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu
2004	J	`jnl`	Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	A buffer planning algorithm based on dead space redistribution. ASP-DAC Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu
2003	—	`conf`	An integrated floorplanning with an efficient buffer planning algorithm. ISPD Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
2003	J	`jnl`	Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu
2003	A*	`conf`	Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	—	`conf`	Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003	J	`jnl`	VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu
2003	—	`conf`	VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. ASP-DAC Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu
2002	J	`jnl`	An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai
2002	—	`conf`	Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	—	`conf`	ECBL: an extended corner block list with solution space including optimum placement. ISPD Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
2001	A*	`conf`	Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	J	`jnl`	Floorplanning with abutment constraints based on corner block list. Integr. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2001	—	`conf`	VLSI block placement using less flexibility first principles. ASP-DAC Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu
2001	—	`conf`	VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
2000	A	`conf`	Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu