Shenggao Li

17 papers Journal 4Unranked 13
YearRankTypeTitle / Venue / Authors
2026 — conf
8.2 A 32Gb/s 12.35Tb/s/mm
ISSCC
Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Han-Tzung Ke, Jie-Ren Huang, Chang-Yi Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen-Ming Chen, Kenny Cheng-Hsiang Hsieh
2025 — conf
36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating.
ISSCC
Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Chih Chen, Wen-Hung Huang, Yu-Chi Chen, Yu-Jie Huang, Alan J. Drake, Chin-Hua Wen, Paul Ranucci, Hsin-Hung Kuo, Aidong Yin, Shu-Chun Yang, Farsheed Mahmoudi, Han-Tzung Ke, Chao-Chieh Li, Nai-Chen Cheng, Jimmy Wang, Kevin Lin, Harry Liao, Jie-Ren Huang, Meng-Hsuan Wu, Kenny Cheng-Hsiang Hsieh, Nicholas Amatruda, William Polanco, David King, Todd Basso, Anwar Kashem
2025 J jnl
Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response for Statistical BER Analysis in Chiplet Interconnects and Beyond.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Shenggao Li, Maher Amer
2025 — conf
TSMC in the Silicon Photonics Era - an Electrical Perspective.
OFC
Mikael Sahrling, Shenggao Li, Frank Lee, Stefan Rusu
2025 — conf
UCle-Compliant Chiplet Interconnect Design Leveraging Cutting-Edge Packaging Technologies.
CICC
Yu-Jie Huang, Mu-Shan Lin, Chien-Chun Tsai, Wei-Chih Chen, Hsin-Hung Kuo, Shu-Chun Yang, Shenggao Li
2024 — conf
A 0.296pJ/bit 17.9Tb/s/mm
VLSI Technology and Circuits
Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, Chin-Hua Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee
2024 — conf
Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process.
VLSI Technology and Circuits
Chu-En Hsia, Chin-Ho Chang, Yung-Shun Chen, Po-Yu Lai, Ching Lin Jen, Yung-Chow Peng, Shenggao Li
2022 — conf
Interconnect in the Era of 3DIC.
CICC
Shenggao Li, Mu-Shan Lin, Wei-Chih Chen, Chien-Chun Tsai
2021 — conf
Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling.
A-SSCC
Shenggao Li, Chien-Chun Tsai, Eric Soenen, Frank J. C. Lee, Cheng-Hsiang Hsieh
2018 — conf
A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.
A-SSCC
Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-Hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton
2015 J jnl
A 22 nm 15-Core Enterprise Xeon® Processor Family.
IEEE J. Solid State Circuits
Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
2014 — conf
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.
ISSCC
Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
2011 — conf
Clock generation for a 32nm server processor with scalable cores.
ISSCC
Shenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia
2003 J jnl
A 10-GHz CMOS quadrature LC-VCO for multirate optical applications.
IEEE J. Solid State Circuits
Shenggao Li, Issy Kipnis, Mohammed Ismail
1999 — conf
A Lower Power CMOS Micromixer for GHz Wireless Applications.
VLSI
Yue Wu, Shenggao Li, Mohammed Ismail, Håkan K. Olsson
1999 — conf
Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application.
VLSI
Shenggao Li, Yue Wu, Chunlei Shi, Mohammed Ismail
1999 J jnl
The Implementation of a VHDL-AMS to SPICE Converter.
J. VLSI Signal Process.
Shenggao Li, Brian Okoon, Mona Mostafa Hella, Mohammed Ismail, Maya Rubeiz