Shenggang Chen

18 papers A* 1A 1C 3Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2019 A* conf
ANN Based Admission Control for On-Chip Networks.
DAC
Boqian Wang, Zhonghai Lu, Shenggang Chen
2019 J jnl
Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication.
IEEE Trans. Parallel Distributed Syst.
Sheng Ma, Zhong Liu, Shenggang Chen, Libo Huang, Yang Guo, Zhiying Wang, Meidi Zhang
2019 C conf
Hardware Acceleration of Multilayer Perceptron Based on Inter-Layer Optimization.
ICCD
Shenggang Chen, Zhonghai Lu
2019 A conf
Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators.
DATE
Sheng Ma, Yang Guo, Shenggang Chen, Libo Huang, Zhiying Wang
2016 J jnl
Iteration Interleaving-Based SIMD Lane Partition.
ACM Trans. Archit. Code Optim.
Yaohua Wang, Dong Wang, Shuming Chen, Zonglin Liu, Shenggang Chen, Xiaowen Chen, Xu Zhou
2016 — conf
Multi-bit transient fault control for NoC links using 2D fault coding method.
NOCS
Xiaowen Chen, Zhonghai Lu, Yuanwu Lei, Yaohua Wang, Shenggang Chen
2015 — conf
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
ISVLSI
Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen
2015 J jnl
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.
J. Softw.
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen, Man Liao
2015 J jnl
Express Ring: a multi-layer and non-blocking NoC architecture.
IEICE Electron. Express
Chen Li, Sheng Ma, Shenggang Chen, Yang Guo, Peng Wang
2015 J jnl
Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.
J. Electr. Comput. Eng.
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen
2013 J jnl
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property.
Comput. Electr. Eng.
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Shenggang Chen, Huitao Gu
2011 — conf
AIFSP: An Adaptive Instruction Flow Stream Processor.
ISVLSI
Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen
2011 — conf
Design and chip implementation of a heterogeneous multi-core DSP.
ASP-DAC
Shuming Chen, Xiaowen Chen, Yi Xu, Jianghua Wan, Jianzhuang Lu, Xiangyuan Liu, Shenggang Chen
2011 — conf
Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs.
NAS
Sheng Liu, Shuming Chen, Haiyan Chen, Shenggang Chen, Hu Chen
2010 C conf
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.
HPCC
Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang
2010 C conf
Multiple Search Centers Based Fast Motion Estimation Algorithm for H.264/AVC.
PDCAT
Huitao Gu, Shuming Chen, Shuwei Sun, Shenggang Chen, Xiaowen Chen
2010 J jnl
P3-CABAC: A Nonstandard Tri-Thread Parallel Evolution of CABAC in the Manycore Era.
IEEE Trans. Circuits Syst. Video Technol.
Shenggang Chen, Shuming Chen, Shuwei Sun
2010 — conf
Performance impact of SMP-cluster on the On-chip Large-scale Parallel Computing architecture.
IPDPS Workshops
Shenggang Chen, Shuming Chen, Yaming Yin