Shengchang Cai

15 papers Journal 5Unranked 10
YearRankTypeTitle / Venue / Authors
2022 — conf
Automated Tuning for Silicon Photonic Filters.
OFC
Kamran Entesari, Samuel Palermo, Christi Madsen, Gihoon Choo, Ramy Rady, Shengchang Cai, Binhao Wang
2020 — conf
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS.
CICC
Yuanming Zhu, Shengchang Cai, Shiva Kiran, Yang-Hang Fan, Po-Hsuan Chang, Sebastian Hoyos, Samuel Palermo
2020 J jnl
A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques.
IEEE J. Solid State Circuits
Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo
2019 — conf
A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE.
CICC
Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo
2019 — conf
A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS.
CICC
Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo
2019 J jnl
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.
IEEE J. Solid State Circuits
Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo
2018 — conf
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE.
CICC
Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo
2017 J jnl
A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS.
IEEE J. Solid State Circuits
Shengchang Cai, Ehsan Zhian Tabasy, Ayman Shafik, Shiva Kiran, Sebastian Hoyos, Samuel Palermo
2016 J jnl
A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization.
IEEE J. Solid State Circuits
Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee, Sebastian Hoyos, Samuel Palermo
2016 J jnl
CMOS ADC-based receivers for high-speed electrical and optical links.
IEEE Commun. Mag.
Samuel Palermo, Sebastian Hoyos, Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Shiva Kiran, Keytaek Lee
2015 — conf
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS.
ISSCC
Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee, Sebastian Hoyos, Samuel Palermo
2015 — conf
A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS.
VLSIC
Shengchang Cai, Ehsan Zhian Tabasy, Ayman Shafik, Shiva Kiran, Sebastian Hoyos, Samuel Palermo
2015 — conf
Adaptively-tunable RF photonic filters.
MWSCAS
Shengchang Cai, Gihoon Choo, Ehsan Zhian Tabasy, Binhao Wang, Kamran Entesari, Samuel Palermo
2012 — conf
An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling.
MWSCAS
Chixiao Chen, Shengchang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren
2011 — conf
A hardware accelerator for speech recognition applications.
ASICON
Tao Chen, Jiawei Zheng, Xingsi Zhang, Shengchang Cai, Yun Chen