Sheng Liu

33 papers B 2C 3Journal 15Unranked 13
YearRankTypeTitle / Venue / Authors
2024 C conf
LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access.
ISCAS
Lanting Guo, Haiyan Chen, Chen Li, Sheng Liu
2023 J jnl
UNCER: A framework for uncertainty estimation and reduction in neural decoding of EEG signals.
Neurocomputing
Tiehang Duan, Zhenyi Wang, Sheng Liu, Yiyi Yin, Sargur N. Srihari
2022 — conf
A dynamic computational memory address architecture for systolic array CNN accelerators.
HPCC/DSS/SmartCity/DependSys
Min Tang, Sheng Liu
2022 C conf
Adaptive Low-Cost Loop Expansion for Modulo Scheduling.
NPC
Hongli Zhong, Zhong Liu, Sheng Liu, Sheng Ma, Chen Li
2022 J jnl
MT-3000: a heterogeneous multi-zone processor for HPC.
CCF Trans. High Perform. Comput.
Kai Lu, Yaohua Wang, Yang Guo, Chun Huang, Sheng Liu, Ruibo Wang, Jianbin Fang, Tao Tang, Zhaoyun Chen, Biwei Liu, Zhong Liu, Yuanwu Lei, Haiyan Sun
2022 — conf
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications.
HPCC/DSS/SmartCity/DependSys
Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei
2022 B conf
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays.
ICPP
Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu
2022 J jnl
Uncertainty Detection in EEG Neural Decoding Models.
CoRR
Tiehang Duan, Zhenyi Wang, Sheng Liu, Sargur N. Srihari, Hui Yang
2021 J jnl
Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions.
CCF Trans. High Perform. Comput.
Yaohua Wang, Chen Li, Chang Liu, Sheng Liu, Yuanwu Lei, Jian Zhang, Yang Zhang, Yang Guo
2021 B conf
Sparse Matrix-Vector Multiplication Cache Performance Evaluation and Design Exploration.
MASCOTS
Jianfeng Cui, Kai Lu, Sheng Liu
2018 J jnl
A task-based multi-core allocation mechanism for packet acceleration.
IEICE Electron. Express
Zerun Li, Yang Guo, Sheng Liu, Junyang Zhang
2018 — conf
Conflict-Free Block-with-Stride Access of 2D Storage Structure.
ICA3PP (3)
Rui Song, Guozhao Zeng, Sheng Liu, Haiyan Chen
2017 — conf
A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS.
NCCET
Hongbing Tan, Haiyan Chen, Sheng Liu, Xikun Ma, Yaqing Chi
2017 — conf
Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures.
ASAP
Hongbing Tan, Haiyan Chen, Sheng Liu, Jianguo Wu
2017 J jnl
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems.
ACM Trans. Embed. Comput. Syst.
Xiaowen Chen, Zhonghai Lu, Sheng Liu, Shuming Chen
2016 — conf
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs.
ISVLSI
Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu
2016 — conf
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs.
ISVLSI
Sheng Liu, Haiyan Chen, Jianghua Wan, Yaohua Wang
2015 — conf
A New Memory Address Transformation for Continuous-Flow FFT Processors with SIMD Extension.
NCCET
Chao Yang, Haiyan Chen, Sheng Liu, Sheng Ma
2014 J jnl
FT-Matrix: A Coordination-Aware Architecture for Signal Processing.
IEEE Micro
Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning
2013 J jnl
A novel QPP interleaver for parallel turbo decoder.
IEICE Electron. Express
Wei Liu, Shuming Chen, Hu Chen, Yaohua Wang, Sheng Liu, Kai Zhang, Xi Ning
2013 J jnl
Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures.
IEICE Trans. Inf. Syst.
Yaohua Wang, Shuming Chen, Hu Chen, Jianghua Wan, Kai Zhang, Sheng Liu
2012 J jnl
A cost conscious performance model for media processors.
IEICE Electron. Express
Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Hu Chen, Sheng Liu, Xi Ning
2012 J jnl
A novel parallel memory organization supporting multiple access types with matched memory modules.
IEICE Electron. Express
Sheng Liu, Shuming Chen, Hu Chen, Yang Guo
2012 — conf
Architectural Implications for SIMD Processors in the Wireless Communication Domain.
HPCC-ICESS
Yaohua Wang, Kai Zhang, Jianghua Wan, Sheng Liu, Xi Ning, Shuming Chen
2012 J jnl
CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors.
IEICE Electron. Express
Kai Zhang, Shuming Chen, Hu Chen, Yaohua Wang, Xiaowen Chen, Sheng Liu, Wei Liu
2012 J jnl
Control-enhanced power-SIMD.
IEICE Electron. Express
Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu
2012 J jnl
Erratum: Control-enhanced power-SIMD [IEICE Electronics Express Vol.9 (2012), No 14 pp 1147-1152].
IEICE Electron. Express
Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu
2011 — conf
A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding.
NAS
Hu Chen, Sheng Liu, Shuming Chen
2011 — conf
Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs.
ASICON
Kai Zhang, Shuming Chen, Sheng Liu, Yaohua Wang, Junhui Huang
2011 J jnl
LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs.
IEICE Electron. Express
Sheng Liu, Shuming Chen, Xi Ning, Jianghua Wan, Hu Chen, Kai Zhang, Yaohua Wang
2011 — conf
Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle.
NAS
Sheng Liu, Shuming Chen, Jianghua Wan, Haiyan Chen, Yaohua Wang
2011 — conf
Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs.
NAS
Sheng Liu, Shuming Chen, Haiyan Chen, Shenggang Chen, Hu Chen
2010 C conf
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.
HPCC
Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang