Shen-Li Chen - RankMe

28 papers Journal 4Unranked 24

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	ESD/Latch-up Immunities Enhancements of HV NLDMOSs by the Embedded Discrete SCR/Schottky Alternating Arrangement Design at the Drain Side. ICCE-Taiwan Xiu-Yuan Yang, Shen-Li Chen, Ting-En Lin, Hung-Wei Chen, Yi-Mu Lee
2024	—	`conf`	Latchup-reliability Impact of High-Voltage nLDMOSs with the Parasitic Schottky Area Modulation in the Source Side. ICCE-Taiwan Ting-En Lin, Shen-Li Chen, Xiu-Yuan Yang, Hung-Wei Chen, Yi-Mu Lee
2023	—	`conf`	ESD-capability Study of High-voltage nLDMOSs with out the Drift Region DPW Effect. ICCE-Taiwan Xiu-Yuan Yang, Xing-Chen Mai, Shen-Li Chen, Yu-Jie Chung, Jhong-Yi Lai, Ting-En Lin
2023	—	`conf`	High-voltage nLDMOS Drain Side Schottky/SCR Modulations for Enhancement Reliability Capabilities. ICCE-Taiwan Ting-En Lin, Shen-Li Chen, Zhi-Wei Liu, Xing-Chen Mai, Xiu-Yuan Yang, Yu-Jie Chung
2022	—	`conf`	An Investigation of ESD-Enhancement by the Drain-side Embedded SCR Area Modulation for HV pLDMOSs. ICCE-TW Zhi-Wei Liu, Shen-Li Chen, Jhong-Yi Lai, Xing-Chen Mai, Yu-Jie Chung
2022	—	`conf`	ESD Capability Analysis of High-voltage nLDMOSs by the Bulk Terminal Modulation. ICCE-TW Jhong-Yi Lai, Shen-Li Chen, Zhi-Wei Liu, Xing-Chen Mai, Yu-Jie Chung
2021	—	`conf`	ESD-Immunity Impact of HV pLDMOS with Drain-side Embedded Horizontal P-type Schottky Modulations. ICCE-TW Shi-Zhe Hong, Shen-Li Chen, Tien-Yu Lan, Yu-Jie Zhou, Zhi-Wei Liu, Jhong-Yi Lai
2021	—	`conf`	Holding-voltage Improvement of UHV Circular nLDMOS Transistors by the Drain-side SCR Engineering. ICCE-TW Tien-Yu Lan, Shen-Li Chen, Yu-Jie Zhou, Shi-Zhe Hong, Jhong-Yi Lai, Zhi-Wei Liu
2021	—	`conf`	Improved UHV IGBT-Cell for ESD Protection with High Holding Voltage via a 0.5µm BCD Process. ICCE-TW Yu-Jie Zhou, Shen-Li Chen, Tien-Yu Lan, Shi-Zhe Hong, Zhi-Wei Liu, Zhong-Yi Lai
2020	—	`conf`	A Novel SCR-based Schottky Diode and Lightly P-well Additions of HV 60V nLDMOS on ESD Capability. ICCE-TW Sheng-Kai Fan, Shen-Li Chen, Po-Lin Lin, Shi-Zhe Hong, Tien-Yu Lan, Yu-Jie Zhou
2020	—	`conf`	ESD-ability of Circular nLDMOS Transistors of UHV by Super-junction Length Modulation and Concentration Gradient. ICKII Tien-Yu Lan, Shen-Li Chen, Po-Lin Lin, Sheng-Kai Fan, Yu-Jie Zhou, Shi-Zhe Hong, Hung-Wei Chen
2020	—	`conf`	ESD-capability Enhancement of Ultra-high Voltage nLDMOSs by the DPW Discrete Layer. ICKII Yu-Jie Zhou, Shen-Li Chen, Pei-Lin Wu, Po-Lin Lin, Sheng-Kai Fan, Tien-Yu Lan, Shi-Zhe Hong
2020	—	`conf`	ESD-capability Influences of UHV Circular nLDMOS Transistors by the Drain-side Ladder-step STI. ICCE-TW Tien-Yu Lan, Shen-Li Chen, Sheng-Kai Fan, Po-Lin Lin, Yu-Jie Zhou, Shi-Zhe Hong, Hung-Wei Chen
2020	—	`conf`	Improving the ESD Robustness of an Ultra-high Voltage nLDMOS Device with the Embedded Schottky Diode. ICCE-TW Po-Lin Lin, Shen-Li Chen, Sheng-Kai Fan, Tien-Yu Lan, Yu-Jie Zhou, Shi-Zhe Hong
2020	—	`conf`	Strengthened ESD Reliability of HV nLDMOSs with Embedded Horizontal Schottky Devices. ICKII Shi-Zhe Hong, Shen-Li Chen, Sheng-Kai Fan, Po-Lin Lin, Tien-Yu Lan, Yu-Jie Zhou
2019	—	`conf`	Channel- & Drift Region's STI-Lengths Impacts of ESD Immunity in HV 60 V nLDMOS Devices. ICCE-TW Sheng-Kai Fan, Shen-Li Chen, Yu-Lin Jhou, Pei-Lin Wu, Po-Lin Lin
2019	—	`conf`	ESD Immunity Impacts of the Drain-Side Heterojunction Device Addition in HV 60 V n/pLDMOS Devices. GCCE Sheng-Kai Fan, Shen-Li Chen, Yu-Lin Jhou, Pei-Lin Wu, Po-Lin Lin
2019	—	`conf`	ESD-Reliability Investigation ICCE-TW Po-Lin Lin, Shen-Li Chen, Pei-Lin Wu, Yu-Lin Jhou, Sheng-Kai Fan
2019	—	`conf`	Evaluating the Drift-Region Length Effect of nLDMOS on ESD Ability with a TLP Testing System. GCCE Po-Lin Lin, Shen-Li Chen, Pei-Lin Wu, Yu-Lin Jhou, Sheng-Kai Fan
2018	J	`jnl`	Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications. IEICE Trans. Electron. Shen-Li Chen, Yu-Ting Huang, Shawn Chang
2018	J	`jnl`	Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers. Sensors Shen-Li Chen, Yi-Cih Wu
2017	J	`jnl`	Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs. IEICE Trans. Electron. Shen-Li Chen, Yu-Ting Huang, Yi-Cih Wu
2016	—	`conf`	Design on ESD robustness of source-side discrete distribution in the 60-V high-voltage nLDMOS devices. ICCE-TW Shen-Li Chen, Chih-Hung Yang, Chih-Ying Yen, Kuei-Jyun Chen, Yi-Cih Wu, Jia-Ming Lin
2016	—	`conf`	ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions. GCCE Shen-Li Chen, Yu-Ting Huang, Chih-Ying Yen, Kuei-Jyun Chen, Yi-Cih Wu, Jia-Ming Lin, Chih-Hung Yang
2015	—	`conf`	Anti-ESD impacts on 60-V P-channel LDMOS devices as none-ODs zone inserting in the bulk region. ICCE-TW Shen-Li Chen, Shawn Chang, Yu-Ting Huang, Shun-Bao Chang
2015	—	`conf`	By using grey system and Neural-Fuzzy Network methods to obtain the threshold voltage of submicron n-MOSFET DUTs. FSKD Shen-Li Chen, Dun-Ying Shu
2015	—	`conf`	ESD reliability building in 0.25 μm 60-V p-channel LDMOS DUTs with different embedded SCRs. ICCE-TW Shen-Li Chen, Yu-Ting Huang, Shawn Chang, Shun-Bao Chang
2015	J	`jnl`	The Adv. Fuzzy Syst. Shen-Li Chen