Shen-Iuan Liu

216 papers C 1Journal 158Unranked 57
YearRankTypeTitle / Venue / Authors
2026 — conf
A 1.59pJ/b 112Gb/s PAM-4 and 1.06pJ/b 168Gb/s PAM-8 Resistor-Less 7-Bit SST DAC-Based Transmitter with 8-Tap FFE in 28nm CMOS.
ISSCC
Yao-hung Tsai, Ming-Han Chuang, Shen-Iuan Liu
2025 J jnl
A 0.07 pJ/b/dB 36-Gb/s PAM-3 Receiver Using Inductor-Reused CTLE and One-Tap Loop-Unrolled DFE in 22-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pin-Yuan Chiu, Shen-Iuan Liu
2025 J jnl
A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE.
IEEE Trans. Very Large Scale Integr. Syst.
Jhe-En Lin, Shen-Iuan Liu
2025 J jnl
A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Yu-Chi Yen, Shen-Iuan Liu
2025 J jnl
A Gain-Boosting Reference-Double-Sampling PLL Using Tail-Feedback VCO With Implicit Common-mode Resonance.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Ta Wu, Shen-Iuan Liu
2024 J jnl
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-Hao Lan, Shen-Iuan Liu
2024 — conf
A 0.91-pJ/b 20.8-32-Gb/s Reference-Less Sub-Baud-Rate CDR Circuit.
A-SSCC
Yao-hung Tsai, Wen-Chi Huang, Shen-Iuan Liu
2024 J jnl
A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Hsi-Kai Peng, Shen-Iuan Liu
2024 J jnl
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range.
IEEE Trans. Very Large Scale Integr. Syst.
Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu
2024 J jnl
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-Hao Lan, Shen-Iuan Liu
2024 J jnl
A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker.
IEEE Trans. Very Large Scale Integr. Syst.
Jhe-En Lin, Yi-Hao Lan, Shen-Iuan Liu
2024 J jnl
A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan-Pang Huang, Shen-Iuan Liu
2023 J jnl
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation.
IEEE J. Solid State Circuits
Zhi-Heng Kang, Shen-Iuan Liu
2022 J jnl
A 0.0067-mm
IEEE Trans. Very Large Scale Integr. Syst.
Yao-hung Tsai, Shen-Iuan Liu
2022 J jnl
A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit.
IEEE Trans. Circuits Syst. II Express Briefs
Wen-Chi Huang, Shen-Iuan Liu
2022 J jnl
A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator.
IEEE Trans. Circuits Syst. II Express Briefs
Jia-Rong Chang, Shen-Iuan Liu
2022 J jnl
A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu
2022 J jnl
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL.
IEEE Trans. Circuits Syst. II Express Briefs
Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu
2022 J jnl
A Wide-Range FD for Referenceless Baud-Rate CDR Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu
2022 — conf
An Adaptive Digital PLL Based on BBPFD Transition Probability.
VLSI-DAT
Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su, Shen-Iuan Liu
2022 — conf
An Injection-Locked Clock Multiplier With Injection Strength Calibration.
VLSI-DAT
Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu
2021 J jnl
A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu
2021 J jnl
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Yong-Ru Lu, Shen-Iuan Liu, Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, Ying-Hsi Lin
2021 J jnl
A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance.
IEEE Trans. Circuits Syst. II Express Briefs
Shun-Chi Chang, Shen-Iuan Liu
2021 — conf
A Digital Phase-Locked Loop With Background Supply Noise Cancellation.
VLSI-DAT
Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu
2021 J jnl
A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller.
IEEE Trans. Circuits Syst. II Express Briefs
Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu
2021 J jnl
A Type-I PLL With Foreground Loop Bandwidth Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Ming-Han Chou, Shen-Iuan Liu
2021 — conf
An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique.
VLSI-DAT
Guan-Yu Su, Zhi-Heng Kang, Shen-Iuan Liu
2020 J jnl
A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guan-Yu Su, Shen-Iuan Liu
2020 J jnl
A 13.56 MHz Current-Mode Wireless Power Receiver With Energy-Investment Capability.
IEEE Trans. Circuits Syst. II Express Briefs
Chung-Jen Kuo, Shen-Iuan Liu
2020 J jnl
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL.
IEEE Trans. Very Large Scale Integr. Syst.
Ming-Han Chou, Shen-Iuan Liu
2020 — conf
A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT.
VLSI-DAT
Ming-Chia Chang, Min-Hsuan Wu, Shen-Iuan Liu
2020 J jnl
A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration.
IEEE Trans. Very Large Scale Integr. Syst.
Kuan-Lin Fu, Shen-Iuan Liu
2020 J jnl
An Indoor Photovoltaic Energy Harvester Using Time-Based MPPT and On-Chip Photovoltaic Cell.
IEEE Trans. Circuits Syst.
Ming-Chia Chang, Shen-Iuan Liu
2019 J jnl
A 13.4-MHz Relaxation Oscillator With Temperature Compensation.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-An Chang, Shen-Iuan Liu
2019 J jnl
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient.
IEEE Trans. Very Large Scale Integr. Syst.
Cheng-En Hsieh, Shen-Iuan Liu
2019 J jnl
A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Che-Wei Tien, Shen-Iuan Liu
2019 J jnl
A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor.
IEEE Trans. Very Large Scale Integr. Syst.
Yu-Kai Chiu, Shen-Iuan Liu
2019 — conf
A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time.
A-SSCC
Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu
2019 J jnl
An On-Chip Relaxation Oscillator With Comparator Delay Compensation.
IEEE Trans. Very Large Scale Integr. Syst.
Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu
2018 — conf
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control.
A-SSCC
Ye-Sing Luo, Hsing-Hung Lin, Shen-Iuan Liu
2018 J jnl
A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Che-Wei Tien, Shen-Iuan Liu
2018 — conf
Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect.
WOCC
San-Liang Lee, Jyehong Chen, Shen-Iuan Liu, Chang-Fa Yang, Hen-Wai Tsao, Shih-Hsiang Hsu, Chien-Chung Lin, Chun-Liang Yang, Zhong Jie Zhang, Kuan-Lin Fu, Lung Wei Chung, Tomas Pankra
2017 J jnl
A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs.
IEEE Trans. Circuits Syst. II Express Briefs
Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu
2017 J jnl
A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu
2017 J jnl
A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yen-Hsiang Tseng, Che-Wei Yeh, Shen-Iuan Liu
2017 J jnl
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wun-Jian Su, Shen-Iuan Liu
2017 — conf
A 56Gbps PAM-4 optical receiver front-end.
A-SSCC
Kuan-Lin Fu, Shen-Iuan Liu
2017 J jnl
A Voltage Multiplier With Adaptive Threshold Voltage Compensation.
IEEE J. Solid State Circuits
Ye-Sing Luo, Shen-Iuan Liu
2016 — conf
19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation.
ISSCC
Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu
2016 J jnl
A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time.
IEEE Trans. Circuits Syst. II Express Briefs
Liang-Jen Chen, Shen-Iuan Liu
2016 J jnl
A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Liang-Jen Chen, Shen-Iuan Liu
2016 J jnl
A 6.7 MHz to 1.24 GHz 0.0318 mm
IEEE J. Solid State Circuits
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
2016 J jnl
A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques.
IEEE J. Solid State Circuits
Ting-Kuei Kuan, Shen-Iuan Liu
2016 J jnl
A Digital PLL Using Oversampling Delta-Sigma TDC.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Lu Wei, Shen-Iuan Liu
2016 — conf
A digital MDLL using switched biasing technique to reduce low-frequency phase noise.
A-SSCC
Chi-Huan Chiang, Chang-Cheng Huang, Ting-Kuei Kuan, Shen-Iuan Liu
2015 J jnl
A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ting-Kuei Kuan, Shen-Iuan Liu
2015 J jnl
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider.
IEEE Trans. Circuits Syst. II Express Briefs
Kai-Hui Zeng, Ting-Kuei Kuan, Shen-Iuan Liu
2015 J jnl
A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Lu Wei, Ting-Kuei Kuan, Shen-Iuan Liu
2015 — conf
A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction.
VLSIC
Ting-Kuei Kuan, Shen-Iuan Liu
2015 — conf
A digital bang-bang phase-locked loop with bandwidth calibration.
A-SSCC
Chi-Huan Chiang, Chang-Cheng Huang, Shen-Iuan Liu
2014 — conf
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS.
A-SSCC
Cheng-En Hsieh, Shen-Iuan Liu
2014 — conf
A 0.43pJ/bit true random number generator.
A-SSCC
Ting-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu
2014 — conf
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop.
A-SSCC
Chien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu
2014 J jnl
A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA.
IEEE Trans. Circuits Syst. II Express Briefs
Yu-Hsun Chien, Kuan-Lin Fu, Shen-Iuan Liu
2014 — conf
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting.
A-SSCC
Yuan-Fu Lin, Chang-Cheng Huang, Jiunn-Yih Max Lee, Chih-Tien Chang, Shen-Iuan Liu
2014 — conf
A low-input-swing AC-DC voltage multiplier using Schottky diodes.
A-SSCC
Ye-Sing Luo, Shen-Iuan Liu
2014 — conf
A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis.
BHI
Shih-Hsiang Shen, Chung-Yi Ting, Chi-Yun Liu, Hua Cheng, Shen-Iuan Liu, Chih-Ting Lin
2014 J jnl
An All-Digital Despreading Clock Generator.
IEEE Trans. Circuits Syst. II Express Briefs
I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu
2014 J jnl
Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient.
IEEE Trans. Circuits Syst. II Express Briefs
Yu-Hsuan Chiang, Shen-Iuan Liu
2013 J jnl
4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations.
IEEE Trans. Circuits Syst. II Express Briefs
Yan-Yu Lin, Shen-Iuan Liu
2013 J jnl
4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs
Yan-Yu Lin, Shen-Iuan Liu
2013 J jnl
A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection.
IEEE J. Solid State Circuits
Shih-Yuan Kao, Shen-Iuan Liu
2013 J jnl
A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing.
IEEE J. Solid State Circuits
Yi-Chieh Huang, Shen-Iuan Liu
2013 J jnl
A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB.
IEEE Trans. Circuits Syst. II Express Briefs
I-Ting Lee, Kai-Hui Zeng, Shen-Iuan Liu
2013 J jnl
A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection.
IEEE J. Solid State Circuits
Shih-Yuan Kao, Shen-Iuan Liu
2013 J jnl
A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Yu-Hsuan Chiang, Shen-Iuan Liu
2013 J jnl
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
2013 — conf
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing.
ISSCC
I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh
2013 J jnl
An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth.
IEEE Trans. Circuits Syst. I Regul. Pap.
I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu
2013 J jnl
Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS.
IEEE J. Solid State Circuits
Pin-Hao Feng, Shen-Iuan Liu
2013 J jnl
Ultrasonic Power/Data Telemetry and Neural Stimulator With OOK-PM Signaling.
IEEE Trans. Circuits Syst. II Express Briefs
Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu
2013 — conf
Ultrasonic telemetry and neural stimulator with FSK-PWM signaling.
VLSI-DAT
Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu
2012 J jnl
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency.
IEEE Trans. Very Large Scale Integr. Syst.
Kun-Hung Tsai, Shen-Iuan Liu
2012 — conf
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing.
ISSCC
Yi-Chieh Huang, Shen-Iuan Liu
2012 J jnl
A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique.
IEEE Trans. Circuits Syst. II Express Briefs
I-Ting Lee, Hung-Yu Lu, Shen-Iuan Liu
2012 — conf
A 6.7MHz-to-1.24GHz 0.0318mm
ISSCC
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
2012 J jnl
A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology.
IEEE J. Solid State Circuits
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
2012 — conf
A fast-locking phase-locked loop using CP control and gated VCO.
VLSI-DAT
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
2012 J jnl
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu
2012 J jnl
G-Band Injection-Locked Frequency Dividers Using π-type LC Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
I-Ting Lee, Shen-Iuan Liu
2012 J jnl
Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ke-Hou Chen, Shen-Iuan Liu
2012 J jnl
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits
Shen-Iuan Liu, Tsung-Hsien Lin, Woogeun Rhee
2011 — conf
3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS.
A-SSCC
I-Ting Lee, Chiao-Hsing Wang, Shen-Iuan Liu
2011 J jnl
A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Chang-Lin Hsieh, Shen-Iuan Liu
2011 J jnl
A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Bo-Yu Lin, Shen-Iuan Liu
2011 — conf
A 20Gb/s digitally adaptive equalizer/DFE with blind sampling.
ISSCC
Yu-Ming Ying, Shen-Iuan Liu
2011 J jnl
A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Chao-Ching Hung, Shen-Iuan Liu
2011 — conf
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization.
ISSCC
Yi-Chieh Huang, Shen-Iuan Liu
2011 J jnl
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression.
IEEE Trans. Very Large Scale Integr. Syst.
Shih-Yuan Kao, Shen-Iuan Liu
2011 J jnl
A Noise Filtering Technique for Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. II Express Briefs
Chao-Ching Hung, Shen-Iuan Liu
2011 J jnl
A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Jen Huang, Shigeisa Nagayasu, Shen-Iuan Liu
2011 — conf
A leakage-current-recycling phase-locked loop in 65nm CMOS technology.
A-SSCC
I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu
2011 J jnl
Analysis and Design of D-Band Injection-Locked Frequency Dividers.
IEEE J. Solid State Circuits
Bo-Yu Lin, Shen-Iuan Liu
2011 J jnl
Decision Feedback Equalizers Using the Back-Gate Feedback Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Chang-Lin Hsieh, Shen-Iuan Liu
2010 J jnl
A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Yuan Kao, Shen-Iuan Liu
2010 J jnl
A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing.
IEEE Trans. Circuits Syst. II Express Briefs
Mu-Chen Huang, Shen-Iuan Liu
2010 J jnl
A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Yuan Kao, Shen-Iuan Liu
2010 J jnl
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers.
IEEE J. Solid State Circuits
Jian-Hao Lu, Shen-Iuan Liu
2010 J jnl
A Phase-Locked Loop With Background Leakage Current Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Jung-Yu Chang, Shen-Iuan Liu
2009 J jnl
A 1.5 GHz All-Digital Spread-Spectrum Clock Generator.
IEEE J. Solid State Circuits
Sheng-You Lin, Shen-Iuan Liu
2009 J jnl
A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS.
IET Circuits Devices Syst.
Jung-Yu Chang, Shen-Iuan Liu
2009 J jnl
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology.
IEEE Trans. Circuits Syst. II Express Briefs
Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu
2009 J jnl
A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider.
IEEE Trans. Circuits Syst. II Express Briefs
I-Ting Lee, Kun-Hung Tsai, Shen-Iuan Liu
2009 — conf
A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS.
ISSCC
Bo-Yu Lin, Kun-Hung Tsai, Shen-Iuan Liu
2009 C conf
A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage.
ISCAS
Hwei-Yu Lee, Shen-Iuan Liu
2009 J jnl
A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop.
IEEE Trans. Circuits Syst. II Express Briefs
Chi-Nan Chuang, Shen-Iuan Liu
2009 J jnl
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology.
IEEE J. Solid State Circuits
Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu
2009 — conf
A 43.7mW 96GHz PLL in 65nm CMOS.
ISSCC
Kun-Hung Tsai, Shen-Iuan Liu
2009 J jnl
A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Jian-Hao Lu, Shen-Iuan Liu
2009 J jnl
A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator.
IEEE Trans. Circuits Syst. II Express Briefs
Mu-Chen Huang, Shen-Iuan Liu
2009 J jnl
A Leakage-Compensated PLL in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Chao-Ching Hung, Shen-Iuan Liu
2009 J jnl
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu
2009 J jnl
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs
Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu
2009 — conf
A leakage-suppression technique for phase-locked systems in 65nm CMOS.
ISSCC
Chao-Ching Hung, Shen-Iuan Liu
2009 J jnl
An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter.
IEEE Trans. Circuits Syst. II Express Briefs
I-Hsin Wang, Hwei-Yu Lee, Shen-Iuan Liu
2009 J jnl
Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology".
IEEE Trans. Circuits Syst. II Express Briefs
Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu
2008 J jnl
10-Gb/s Inductorless CDRs With Digital Frequency Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Che-Fu Liang, Hong-Lin Chu, Shen-Iuan Liu
2008 — conf
3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology.
ISSCC
Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
2008 J jnl
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS.
IEEE J. Solid State Circuits
Chih-Fan Liao, Shen-Iuan Liu
2008 J jnl
A 0.18-muhbox m CMOS 1.25-Gbps Automatic-Gain-Control Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
I-Hsin Wang, Shen-Iuan Liu
2008 — conf
A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells.
ISSCC
Che-Fu Liang, Shen-Iuan Liu
2008 J jnl
A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Chi-Nan Chuang, Shen-Iuan Liu
2008 J jnl
A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery.
IEEE J. Solid State Circuits
Chih-Fan Liao, Shen-Iuan Liu
2008 — conf
A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR.
ISSCC
Chih-Fan Liao, Shen-Iuan Liu
2008 J jnl
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu
2008 J jnl
A Delay-Locked Loop With Statistical Background Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Shao-Ku Kao, Shen-Iuan Liu
2008 J jnl
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems.
IEEE J. Solid State Circuits
Che-Fu Liang, Shin-Hua Chen, Shen-Iuan Liu
2008 J jnl
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector.
IEEE J. Solid State Circuits
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
2008 J jnl
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu
2008 J jnl
An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line.
IEEE J. Solid State Circuits
Chao-Chyun Chen, Shen-Iuan Liu
2008 J jnl
Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array.
IET Circuits Devices Syst.
Wei-Jen Huang, Shen-Iuan Liu
2008 J jnl
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs.
IEEE Trans. Circuits Syst. II Express Briefs
Shao-Hung Lin, Shen-Iuan Liu
2008 J jnl
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits
Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee
2007 J jnl
A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump.
IEEE Trans. Circuits Syst. II Express Briefs
Chi-Nan Chuang, Shen-Iuan Liu
2007 J jnl
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology.
IEEE J. Solid State Circuits
Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu
2007 — conf
A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology.
SoCC
Hwei-Yu Lee, Shen-Iuan Liu
2007 — conf
A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry.
CICC
Ke-Hou Chen, Jian-Hao Lu, Shen-Iuan Liu
2007 J jnl
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Shen-Iuan Liu
2007 — conf
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS.
ISSCC
Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu
2007 J jnl
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Shen-Iuan Liu
2007 — conf
A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology.
ISSCC
Chi-Nan Chuang, Shen-Iuan Liu
2007 — conf
A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS.
ISSCC
Chih-Fan Liao, Shen-Iuan Liu
2007 — conf
A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS.
ISSCC
Chihun Lee, Shen-Iuan Liu
2007 J jnl
A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop.
IEEE Trans. Circuits Syst. II Express Briefs
Shao-Ku Kao, Bo-Jiun Chen, Shen-Iuan Liu
2007 — conf
A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS.
SoCC
Hwei-Yu Lee, I-Hsin Wang, Shen-Iuan Liu
2007 J jnl
A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers.
IEEE J. Solid State Circuits
Chih-Fan Liao, Shen-Iuan Liu
2007 J jnl
A DLL-Based Variable-Phase Clock Buffer.
IEEE Trans. Circuits Syst. II Express Briefs
Chao-Chyun Chen, Jung-Yu Chang, Shen-Iuan Liu
2007 J jnl
A Low-Jitter Spread Spectrum Clock Generator Using FDMP.
IEEE Trans. Circuits Syst. II Express Briefs
Ding-Shiuan Shen, Shen-Iuan Liu
2007 J jnl
A Multi-Band Burst-Mode Clock and Data Recovery Circuit.
IEICE Trans. Electron.
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
2007 J jnl
A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time.
IEEE Trans. Circuits Syst. II Express Briefs
Sung-Rung Han, Chi-Nan Chuang, Shen-Iuan Liu
2007 J jnl
An Ultra-Wide-Band 0.4-10-GHz LNA in 0.18-μm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Ke-Hou Chen, Jian-Hao Lu, Bo-Jiun Chen, Shen-Iuan Liu
2007 J jnl
Spur-Suppression Techniques for Frequency Synthesizers.
IEEE Trans. Circuits Syst. II Express Briefs
Che-Fu Liang, Hsin-Hua Chen, Shen-Iuan Liu
2006 J jnl
A 0.7-2-GHz self-calibrated multiphase delay-locked loop.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Jung-Yu Chang, Chun-Yi Kuo, Shen-Iuan Liu
2006 J jnl
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology.
IEICE Trans. Electron.
Chi-Nan Chuang, Shen-Iuan Liu
2006 — conf
A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet.
ISSCC
Chih-Fan Liao, Shen-Iuan Liu
2006 — conf
A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS.
CICC
Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
2006 — conf
A 14-band Frequency Synthesizer for MB-OFDM UWB Application.
ISSCC
Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, Gin-Kou Ma
2006 J jnl
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Kuan-Hua Chao, Sy-Chyuan Hwu, Chuan-Kang Liang, Shen-Iuan Liu
2006 J jnl
A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rong-Jyi Yang, Kuan-Hua Chao, Shen-Iuan Liu
2006 — conf
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology.
CICC
Chihun Lee, Lan-Chou Cho, Shen-Iuan Liu
2006 J jnl
A Calibrated Pulse Generator for Impulse-Radio UWB Applications.
IEEE J. Solid State Circuits
Che-Fu Liang, Shih-Tsai Liu, Shen-Iuan Liu
2006 J jnl
A spur-reduction technique for a 5-GHz frequency synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chun-Yi Kuo, Jung-Yu Chang, Shen-Iuan Liu
2006 J jnl
All-Digital Clock Deskew Buffer with Variable Duty Cycles.
IEICE Trans. Electron.
Shao-Ku Kao, Shen-Iuan Liu
2006 J jnl
All-Digital Fast-Locked Synchronous Duty-Cycle Corrector.
IEEE Trans. Circuits Syst. II Express Briefs
Shao-Ku Kao, Shen-Iuan Liu
2006 J jnl
All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles.
IEEE J. Solid State Circuits
You-Jen Wang, Shao-Ku Kao, Shen-Iuan Liu
2005 — conf
A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications.
ISCAS (1)
Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, Hen-Wai Tsao
2005 J jnl
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector.
IEICE Trans. Electron.
Rong-Jyi Yang, Shen-Iuan Liu
2005 J jnl
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs.
IEICE Trans. Electron.
Rong-Jyi Yang, Shen-Iuan Liu
2005 — conf
A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver.
CICC
Chih-Fan Liao, Shen-Iuan Liu
2005 J jnl
A single-path pulsewidth control loop with a built-in delay-locked loop.
IEEE J. Solid State Circuits
Sung-Rung Han, Shen-Iuan Liu
2005 — conf
A tunable bandpass ΔΣ modulator using double sampling.
ISCAS (4)
Chien-Hung Kuo, Chang-Hung Chen, Huang-Shih Lin, Shen-Iuan Liu
2005 J jnl
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Shen-Iuan Liu
2005 J jnl
CMOS current-mode divider and its applications.
IEEE Trans. Circuits Syst. II Express Briefs
Weihsing Liu, Shen-Iuan Liu, Shui-Ken Wei
2005 J jnl
CMOS wideband amplifiers using multiple inductive-series peaking technique.
IEEE J. Solid State Circuits
Chia-Hsin Wu, Chih-Hun Lee, Wei-Sheng Chen, Shen-Iuan Liu
2005 J jnl
Selective metal parallel shunting inductor and its VCO application.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chia-Hsin Wu, Chun-Yi Kuo, Shen-Iuan Liu
2004 J jnl
A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps.
IEEE J. Solid State Circuits
Chien-Hung Kuo, Shen-Iuan Liu
2004 — conf
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors.
ISCAS (1)
Chia-Hsin Wu, Jieh-Wei Liao, Shen-Iuan Liu
2004 J jnl
A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet.
IEEE J. Solid State Circuits
Rong-Jyi Yang, Shang-Ping Chen, Shen-Iuan Liu
2004 J jnl
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle.
IEEE J. Solid State Circuits
Sung-Rung Han, Shen-Iuan Liu
2004 J jnl
A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC.
IEEE J. Solid State Circuits
Ming-Huang Liu, Kuo-Chan Huang, Wei-Yang Ou, Tsung-Yi Su, Shen-Iuan Liu
2004 J jnl
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hsiang-Hui Chang, Rong-Jyi Yang, Shen-Iuan Liu
2003 J jnl
A fast locking and low jitter delay-locked loop using DHDL.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu
2003 — conf
A shifted-averaging VCO with precise multiphase outputs and low jitter operation.
ESSCIRC
Hsiang-Hui Chang, Shang-Ping Chen, Shen-Iuan Liu
2003 J jnl
A spread-spectrum clock generator with triangular modulation.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, I-Hui Hua, Shen-Iuan Liu
2003 J jnl
Analysis of on-chip spiral inductors using the distributed capacitance model.
IEEE J. Solid State Circuits
Chia-Hsin Wu, Chih-Chun Tang, Shen-Iuan Liu
2003 J jnl
CMOS Tunable 1/
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Weihsing Liu, Shen-Iuan Liu
2002 — conf
A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay.
CICC
Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu
2002 J jnl
A wide-range delay-locked loop with a fixed latency of one clock cycle.
IEEE J. Solid State Circuits
Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu
2002 — conf
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network.
ISCAS (3)
Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu
2002 J jnl
Miniature 3-D inductors in standard CMOS process.
IEEE J. Solid State Circuits
Chih-Chun Tang, Chia-Hsin Wu, Shen-Iuan Liu
2001 J jnl
A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme.
IEEE J. Solid State Circuits
Wei-Hung Chen, Guang-Kaai Dehang, Jong-Woei Chen, Shen-Iuan Liu
2001 — conf
A fast-lock mixed-mode DLL using a 2-b SAR algorithm.
CICC
Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu
2001 J jnl
A fast-lock mixed-mode DLL using a 2-b SAR algorithm.
IEEE J. Solid State Circuits
Guang-Kaai Dehng, Jyh-Woei Lin, Shen-Iuan Liu
2001 J jnl
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques.
IEEE J. Solid State Circuits
Ching-Yuan Yang, Shen-Iuan Liu
2001 J jnl
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique.
IEEE J. Solid State Circuits
Ming-Huang Liu, Shen-Iuan Liu
2001 — conf
CMOS oversampling Sigma-Delta magnetic to digital converters.
ISCAS (1)
Lee-An Ho, Shr-Lung Chen, Chien-Hung Kuo, Shen-Iuan Liu
2001 J jnl
CMOS oversampling ΔΣ magnetic-to-digital converters.
IEEE J. Solid State Circuits
Chien-Hung Kuo, Shr-Lung Chen, Lee-An Ho, Shen-Iuan Liu
2000 J jnl
A 900-MHz 1-V CMOS frequency synthesizer.
IEEE J. Solid State Circuits
Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, Shen-Iuan Liu
2000 J jnl
A double-sampling pseudo-two-path bandpass ΔΣ modulator.
IEEE J. Solid State Circuits
Shen-Iuan Liu, Chien-Hung Kuo, Ruey-Yuan Tsai, Jingshown Wu
2000 J jnl
Clock-deskew buffer using a SAR-controlled delay-locked loop.
IEEE J. Solid State Circuits
Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang, Shen-Iuan Liu
2000 J jnl
Fast-switching frequency synthesizer with a discriminator-aided phase detector.
IEEE J. Solid State Circuits
Ching-Yuan Yang, Shen-Iuan Liu
1999 — conf
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution.
CICC
Poki Chen, Shen-Iuan Liu
1999 J jnl
Low-power clock-deskew buffer for high-speed digital circuits.
IEEE J. Solid State Circuits
Shen-Iuan Liu, Jiunn-Hwa Lee, Hen-Wai Tsao
1998 J jnl
New dynamic flip-flops for high-speed dual-modulus prescaler.
IEEE J. Solid State Circuits
Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu
1994 J jnl
CMOS four-quadrant multiplier using bias feedback techniques.
IEEE J. Solid State Circuits
Shen-Iuan Liu, Yuh-Shyan Hwang