Shen-Fu Hsiao - RankMe

83 papers C 20Misc 5Journal 25Unranked 33

Year	Rank	Type	Title / Venue / Authors
2024	C	`conf`	Hardware Accelerator for MobileViT Vision Transformer with Reconfigurable Computation. ISCAS Shen-Fu Hsiao, Tzu-Hsien Chao, Yen-Che Yuan, Kun-Chih Chen
2024	C	`conf`	Neural Network Acceleration Using Digit-Plane Computation with Early Termination. ISCAS Shen-Fu Hsiao, Hou-Chun Kuo, Yu Kuo, Kun-Chih Chen
2022	J	`jnl`	A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh
2022	—	`conf`	A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu
2022	C	`conf`	Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination. ISCAS Shen-Fu Hsiao, Hung-Ching Li, Yu-Che Yen, Po-Chang Li
2021	C	`conf`	Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. ISCAS Shen-Fu Hsiao, Jian-Ming Chen, Yu-Hong Chen, Hung-Ching Li, Yi Hsu
2021	—	`conf`	Efficient Computation of Depthwise Separable Convolution in MoblieNet Deep Neural Network Models. ICCE-TW Shen-Fu Hsiao, Bo-Ching Tsai
2021	C	`conf`	Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning. ISCAS Shen-Fu Hsiao, Yu-Chang Chen, Yu-Che Yen
2021	—	`conf`	Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage. ICCE-TW Shen-Fu Hsiao, Jyun-Liang Chen, Yi Hsu, Xiang-Ting Huang
2021	—	`conf`	Quantization of Deep Neural Network Models Considering Per-Layer Computation Complexity for Efficient Execution in Multi-Precision Accelerators. ICCE-TW Shen-Fu Hsiao, Yu-Che Yen
2020	J	`jnl`	Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. Shen-Fu Hsiao, Kun-Chih Chen, Chih-Chien Lin, Hsuan-Jui Chang, Bo-Ching Tsai
2020	—	`conf`	Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication. VLSI-DAT Shen-Fu Hsiao, Yu-Hong Chen
2020	C	`conf`	Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation. ISCAS Shen-Fu Hsiao, Chia-Yang Wong, Yu-Chang Chen
2020	C	`conf`	Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations. ISCAS Shen-Fu Hsiao, Hsuan-Jui Chang
2019	C	`conf`	Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse. ISCAS Shen-Fu Hsiao, Pei-Hsuan Wu, Jien-Min Chen, Kun-Chih Chen
2019	—	`conf`	Low-Complexity Deep Neural Networks for Image Object Classification and Detection. APCCAS Shen-Fu Hsiao, Jing-Fu Zhan, Chih-Chien Lin
2019	—	`conf`	Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks. APCCAS Shen-Fu Hsiao, Kuey-Chin Huang, Yu-Hong Chen
2018	C	`conf`	Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks. DSD Shen-Fu Hsiao, Yu-Chang Chen, Hsiang-Hao Liang
2018	—	`conf`	Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators. GCCE Shen-Fu Hsiao, Pei-Hsuen Wu
2018	C	`conf`	Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels. DSD Shen-Fu Hsiao, Chen-Yen Tsai
2018	—	`conf`	Hardware design of disparity computation for stereo vision using guided image filtering. VLSI-DAT Shen-Fu Hsiao, Chih-Hsuan Chang
2018	C	`conf`	Optimization of Lookup Table Size in Table-Bound Design of Function Computation. ISCAS Shen-Fu Hsiao, Kun-Chih Chen, Yi-Hau Chen
2017	—	`conf`	Hardware efficient implementation of histograms of oriented gradients for pedestrian detection. GCCE Shen-Fu Hsiao, Tz-Heng Tz-Heng You
2017	J	`jnl`	Hierarchical Multipartite Function Evaluation. IEEE Trans. Computers Shen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang
2016	—	`conf`	Hardware design of histograms of oriented gradients based on local binary pattern and binarization. APCCAS Shen-Fu Hsiao, Jun-Mao Chan, Ching-Hui Wang
2016	—	`conf`	Low-power dual-precision table-based function evaluation supporting dynamic precision changes. APCCAS Shen-Fu Hsiao, Kuei-Chun Huang
2015	—	`conf`	An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee
2015	—	`conf`	Low-power and high-performance design of OpenGL ES 2.0 graphics processing unit for mobile applications. DSP Shen-Fu Hsiao, Shang-Yu Li, Kai-Hsiang Tsao
2015	J	`jnl`	Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. IEEE Trans. Circuits Syst. II Express Briefs Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher
2014	C	`conf`	Compression of Lookup Table for Piecewise Polynomial Function Evaluation. DSD Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu
2014	C	`conf`	Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning. DSD Shen-Fu Hsiao, Guan-Fu Yeh, Je-Chi Chen
2014	C	`conf`	Design of low-leakage multi-port SRAM for register file in graphics processing unit. ISCAS Shen-Fu Hsiao, Pu-Cheng Wu
2014	—	`conf`	VLSI implementation of belief-propagation-based stereo matching with linear-model message update. APCCAS Shen-Fu Hsiao, Jun-Ming Huang, Po-Sheng Wu
2014	—	`conf`	VLSI implementations of stereo matching using Dynamic Programming. VLSI-DAT Shen-Fu Hsiao, Wen-Ling Wang, Po-Sheng Wu
2013	J	`jnl`	Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. IEEE Trans. Very Large Scale Integr. Syst. Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen
2013	—	`conf`	Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. VLSI-DAT Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen
2013	J	`jnl`	Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation. IEEE Trans. Circuits Syst. II Express Briefs Shen-Fu Hsiao, Jun-Hong Zhang Jian, Ming-Chih Chen
2012	—	`conf`	Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. APCCAS Shen-Fu Hsiao, Chi-Guang Lin, Po-Han Wu, Chia-Sheng Wen
2012	C	`conf`	Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling. ISCAS Shen-Fu Hsiao, Jin-Wen Cheng, Wen-Ling Wang, Guan-Fu Yeh
2012	—	`conf`	Low-cost designs of rectangular to polar coordinate converters for digital communication. APCCAS Shen-Fu Hsiao, Chia-Sheng Wen, Cheng-Han Lee, Andrew Lee
2012	J	`jnl`	Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. IEEE Trans. Circuits Syst. II Express Briefs Shen-Fu Hsiao, Hou-Jen Ko, Chia-Sheng Wen
2011	J	`jnl`	Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding. IEEE Trans. Circuits Syst. II Express Briefs Hou-Jen Ko, Shen-Fu Hsiao
2011	—	`conf`	Designs of angle-rotation in digital frequency synthesizer/mixer using multi-stage architectures. ACSCC Shen-Fu Hsiao, Cheng-Han Lee, Yen-Chun Cheng, Andrew Lee
2010	C	`conf`	A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation. ISCAS Hou-Jen Ko, Shen-Fu Hsiao, Wen-Liang Huang
2010	—	`conf`	Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method. APCCAS Shen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen
2010	J	`jnl`	Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. IEEE Trans. Circuits Syst. II Express Briefs Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
2009	—	`conf`	An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang
2009	J	`jnl`	Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ming-Chih Chen, Shen-Fu Hsiao
2008	C	`conf`	An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. ISCAS Shen-Fu Hsiao, Ping-Chung Wei, Ching-Pin Lin
2008	C	`conf`	Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ISCAS Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
2008	—	`conf`	Efficient designs of flaoting-point CORDIC rotation and vectoring operations. APCCAS Shen-Fu Hsiao, Hsin-Mau Lee, Yen-Chun Cheng, Ming-Yu Tsai
2008	—	`conf`	Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation. APCCAS Shen-Fu Hsiao, Yuan-Nan Chang, Tze-Ching Tien, Kun-Chih Chen
2006	—	`conf`	An Automatic Cache Generator Based on Content-Addressable Memory. APCCAS Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chong Cheng, Ming-Yu Tsai
2006	—	`conf`	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. APCCAS Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
2006	J	`jnl`	Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations. IEEE Trans. Circuits Syst. I Regul. Pap. Shen-Fu Hsiao, Ming-Chih Chen, Chia-Shin Tu
2006	—	`conf`	Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. MTDT Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng
2005	J	`jnl`	A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. IEICE Trans. Inf. Syst. Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai, Jenq-Shiun Jan
2005	—	`conf`	An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ISCAS (3) Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen
2005	J	`jnl`	Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design. IEEE Trans. Circuits Syst. I Regul. Pap. Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang, Cheng-Han Lee
2005	J	`jnl`	Low-error carry-free fixed-width multipliers with low-cost compensation circuits. IEEE Trans. Circuits Syst. II Express Briefs Tso-Bing Juang, Shen-Fu Hsiao
2004	J	`jnl`	A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations. IEEE Signal Process. Lett. Shen-Fu Hsiao, Yu Hen Hu, Tso-Bing Juang
2004	J	`jnl`	Para-CORDIC: parallel CORDIC rotation algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. Tso-Bing Juang, Shen-Fu Hsiao, Ming-Yu Tsai
2003	—	`conf`	Design and implementation of a video-oriented network-interface-card system. ASP-DAC Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang
2002	J	`jnl`	High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic. VLSI Design Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen
2002	—	`conf`	Partition methodology for the final adder in a tree-structure parallel multiplier generator. APCCAS (1) Tso-Bing Juang, Jeng-Hsiun Jan, Ming-Yu Tsai, Shen-Fu Hsiao
2001	J	`jnl`	A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array. IEEE Trans. Circuits Syst. Video Technol. Shen-Fu Hsiao, Wei-Ren Shiue
2001	J	`jnl`	Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec. J. VLSI Signal Process. Shen-Fu Hsiao, Jian-Ming Tseng
2000	C	`conf`	High-performance multiplexer-based logic synthesis using pass-transistor logic. ISCAS Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen
2000	Misc	`conf`	Low-cost unified architectures for the computation of discrete trigonometric transforms. ICASSP Shen-Fu Hsiao, Wei-Ren Shiue
2000	J	`jnl`	Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD. J. VLSI Signal Process. Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme
2000	J	`jnl`	VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking. IEEE Trans. Consumer Electron. Shen-Fu Hsiao, Yor-Chin Tai, Kai-Hsiang Chang
1999	J	`jnl`	A cost-efficient and fully-pipelinable architecture for DCT/IDCT. IEEE Trans. Consumer Electron. Shen-Fu Hsiao, Wei-Ren Shiue, Jian-Ming Tseng
1999	—	`conf`	A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations. ISCAS (1) Shen-Fu Hsiao
1999	Misc	`conf`	A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation. ICASSP Shen-Fu Hsiao, Wei-Ren Shiue
1999	—	`conf`	Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology. ICECS Chua-Chin Wang, Sheng-Hua Chen, Shen-Fu Hsiao, Chuan-lin Wu
1999	Misc	`conf`	New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array. ICASSP Shen-Fu Hsiao, Wei-Ren Shiue
1998	J	`jnl`	Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure. J. VLSI Signal Process. Shen-Fu Hsiao, Jen-Yin Chen
1997	Misc	`conf`	New unified VLSI architectures for computing DFT and other transforms. ICASSP Shen-Fu Hsiao, Chung-Yi Yen
1996	J	`jnl`	Parallel singular value decomposition of complex matrices using multidimensional CORDIC algorithms. IEEE Trans. Signal Process. Shen-Fu Hsiao, Jean-Marc Delosme
1995	Misc	`conf`	Adaptive Jacobi method for parallel singular value decompositions. ICASSP Shen-Fu Hsiao
1995	J	`jnl`	Householder CORDIC Algorithms. IEEE Trans. Computers Shen-Fu Hsiao, Jean-Marc Delosme
1994	—	`conf`	Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms. ASAP Shen-Fu Hsiao, Jean-Marc Delosme
1991	C	`conf`	The CORDIC Householder algorithm. IEEE Symposium on Computer Arithmetic Shen-Fu Hsiao, Jean-Marc Delosme