Sheldon B. Akers Jr.

26 papers A* 2A 1B 2Journal 16Unranked 5
YearRankTypeTitle / Venue / Authors
1990 A conf
Why is less information from logic simulation more useful in fault simulation?
ITC
Sheldon B. Akers Jr., Sungju Park, Balakrishnan Krishnamurthy, Ashok Swaminathan
1989 J jnl
A Group-Theoretic Model for Symmetric Interconnection Networks.
IEEE Trans. Computers
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
1989 J jnl
Test counting: a tool for VLSI testing.
IEEE Des. Test
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
1987 J jnl
On Group Graphs and Their Fault Tolerance.
IEEE Trans. Computers
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
1987 B conf
The Star Graph: An Attractive Alternative to the n-Cube.
ICPP
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy, Dov Harel
1986 B conf
: A Group Theoretic Model for Symmetric Interconnection Networks.
ICPP
Sheldon B. Akers Jr., Balakrishnan Krishnamurthy
1984 J jnl
On the Complexity of Estimating the Size of a Test Set.
IEEE Trans. Computers
Balakrishnan Krishnamurthy, Sheldon B. Akers Jr.
1981 A* conf
On the use of the linear assignment algorithm in module placement.
DAC
Sheldon B. Akers Jr.
1980 J jnl
Test Generation Techniques.
Computer
Sheldon B. Akers Jr.
1978 J jnl
Binary Decision Diagrams.
IEEE Trans. Computers
Sheldon B. Akers Jr.
1976 J jnl
A Logic System for Fault Test Generation.
IEEE Trans. Computers
Sheldon B. Akers Jr.
1974 J jnl
Fault Diagnosis as a Graph Coloring Problem.
IEEE Trans. Computers
Sheldon B. Akers Jr.
1973 J jnl
Universal Test Sets for Logic Networks.
IEEE Trans. Computers
Sheldon B. Akers Jr.
1972 J jnl
A Rectangular Logic Array.
IEEE Trans. Computers
Sheldon B. Akers Jr.
1972 — conf
Universal Test Sets for Logic Networks
SWAT
Sheldon B. Akers Jr.
1971 — conf
A Rectangular Logic Array
SWAT
Sheldon B. Akers Jr.
1970 A* conf
IC mask layout with a single conductor layer.
DAC
Sheldon B. Akers Jr., James M. Geyer, Donald L. Roberts
1970 J jnl
R70-40 Module Clustering to Minimize Delay in Digital Networks.
IEEE Trans. Computers
Sheldon B. Akers Jr.
1968 J jnl
On Maximum Inversion with Minimum Inverters.
IEEE Trans. Computers
Sheldon B. Akers Jr.
1965 J jnl
A Diagrammatic Approach to Multilevel Logic Synthesis.
IEEE Trans. Electron. Comput.
Sheldon B. Akers Jr.
1965 J jnl
On the Construction of (d, k) Graphs.
IEEE Trans. Electron. Comput.
Sheldon B. Akers Jr.
1964 — conf
A diagrammatic approach to multi-level logic synthesis
SWCT
Sheldon B. Akers Jr.
1962 — conf
Synthesis of combinational logic using three-input majority gates
SWCT
Sheldon B. Akers Jr.
1961 J jnl
A Truth Table Method for the Synthesis of Combinational Logic.
IRE Trans. Electron. Comput.
Sheldon B. Akers Jr.
1961 — conf
Threshold logic and two-person, zero-sum games
SWCT
Sheldon B. Akers Jr.
1955 J jnl
A Non-Numerical Approach to Production Scheduling Problems.
Oper. Res.
Sheldon B. Akers Jr., Joyce Friedman