Shekhar Borkar

106 papers A* 17A 15C 3Misc 2Journal 36Unranked 32

Year	Rank	Type	Title / Venue / Authors
2021	A	`conf`	Security Closure of Physical Layouts ICCAD Special Session Paper. ICCAD Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri
2017	J	`jnl`	Traleika Glacier: A hardware-software co-designed approach to exascale computing. Parallel Comput. Vincent Cavé, Romain Cledat, Paul Griffin, Ankit More, Bala Seshasayee, Shekhar Borkar, Sanjay Chatterjee, Dave Dunning, Joshua B. Fryman
2016	—	`ch.`	Extreme Energy Efficiency by Near Threshold Voltage Operation. Near Threshold Computing Shekhar Borkar
2015	J	`jnl`	A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar
2015	—	`conf`	Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs? VLSIC P. Yue, Bing J. Sheu, A. Matsuzawa, K. Asada, L. Loh, Kofi A. A. Makinwa, Shekhar Borkar, Vladimir Stojanovic
2014	—	`conf`	16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De
2014	—	`conf`	Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. CICC Robert Pawlowski, Joseph Crop, Minki Cho, James W. Tschanz, Vivek De, Thomas Fairbanks, Heather Quinn, Shekhar Borkar, Patrick Yin Chiang
2014	—	`conf`	Resiliency for many-core system on a chip. ASP-DAC Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar
2013	J	`jnl`	A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
2013	J	`jnl`	Centip3De demonstrates more than Moore...: technical perspective. Commun. ACM Shekhar Borkar
2013	—	`conf`	EP3: Empowering the killer SoC applications of 2020. ISSCC Shekhar Borkar, Uming Ko, Ali Keshavarzi, Eugenio Cantatore
2013	A	`conf`	Exascale Computing - A Fact or a Fiction? IPDPS Shekhar Borkar
2013	A*	`conf`	Power management and delivery for high-performance microprocessors. DAC Tanay Karnik, Mondira (Mandy) Deb Pant, Shekhar Borkar
2013	A*	`conf`	Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu
2012	—	`conf`	A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
2012	A*	`conf`	Near-threshold voltage (NTV) design: opportunities and challenges. DAC Himanshu Kaul, Mark A. Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2012	Misc	`conf`	On the Role of Co-design in High Performance Computing. High Performance Computing Workshop (2) Richard F. Barrett, Shekhar Borkar, Sudip S. Dosanjh, Simon D. Hammond, Michael A. Heroux, Xiaobo Sharon Hu, Justin Luitjens, Steven G. Parker, John Shalf, Li Tang
2012	—	`conf`	Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee. ISSCC Masaitsu Nakajima, Shekhar Borkar
2011	A*	`conf`	3D integration for energy efficient system design. DAC Shekhar Borkar
2011	—	`conf`	3DICs for tera-scale computing: a case study. ISPD Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
2011	J	`jnl`	A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart
2011	—	`conf`	Integrated inductors with magnetic materials for on-chip power conversion. Hot Chips Symposium Donald S. Gardner, Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Shekhar Borkar
2011	J	`jnl`	Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Comput. Digit. Tech. Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
2011	J	`jnl`	The future of microprocessors. Commun. ACM Shekhar Borkar, Andrew A. Chien
2011	J	`jnl`	Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar
2010	J	`jnl`	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson
2010	—	`conf`	The semiconductor industry in 2025. ISSCC Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva G. Narendra
2010	—	`conf`	Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar
2009	J	`jnl`	2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2009	—	`conf`	A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2009	J	`jnl`	A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. IEEE J. Solid State Circuits Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
2009	A*	`conf`	Design perspectives on 22nm CMOS and beyond. DAC Shekhar Borkar
2008	J	`jnl`	A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. IEEE J. Solid State Circuits Mark A. Anders, Sanu K. Mathew, Steven Hsu, Ram K. Krishnamurthy, Shekhar Borkar
2008	—	`conf`	A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. ESSCIRC Mark A. Anders, Himanshu Kaul, Martin Hansson, Ram Krishnamurthy, Shekhar Borkar
2008	—	`conf`	A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2008	J	`jnl`	An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE J. Solid State Circuits Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar
2008	A*	`conf`	Custom is from Venus and synthesis from Mars. DAC Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye
2008	J	`jnl`	Thousand-Core Chips [Roundtable]. IEEE Des. Test Comput. David Yeh, Li-Shiuan Peh, Shekhar Borkar, John A. Darringer, Anant Agarwal, Wen-mei W. Hwu
2007	—	`conf`	A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. ISSCC Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2007	J	`jnl`	A 5-GHz Mesh Interconnect for a Teraflops Processor. IEEE Micro Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar
2007	A	`conf`	Future of on-chip interconnection architectures. ISLPED Shekhar Borkar, William J. Dally
2007	A	`conf`	Microprocessors in the era of terascale integration. DATE Shekhar Borkar, Norman P. Jouppi, Per Stenström
2007	A*	`conf`	Thousand Core ChipsA Technology Perspective. DAC Shekhar Borkar
2006	J	`jnl`	A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2006	—	`conf`	An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. ISSCC Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy, Shekhar Borkar
2006	A*	`conf`	Electronics beyond nano-scale CMOS. DAC Shekhar Borkar
2006	C	`conf`	Introduction to panel discussion Probabilistic & statistical design - the wave of the future. VLSI-SoC Shekhar Borkar
2006	—	`conf`	Probabilistic amp; Statistical Design - the Wave of the Future. VLSI-SoC (Selected Papers) Shekhar Borkar
2006	J	`jnl`	Tackling variability and reliability challenges. IEEE Des. Test Comput. Shekhar Borkar
2006	A*	`conf`	Tomorrow's analog: just dead or just different? DAC Shekhar Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles G. Sodini
2005	J	`jnl`	A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. IEEE J. Solid State Circuits Peter Hazucha, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Paul Hack, Gregory E. Dermer, Siva G. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar
2005	J	`jnl`	A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. IEEE J. Solid State Circuits Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang
2005	J	`jnl`	A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. IEEE J. Solid State Circuits Sanu K. Mathew, Mark A. Anders, Brad Bloechel, Trang Nguyen, Ram K. Krishnamurthy, Shekhar Borkar
2005	A	`conf`	An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Borkar
2005	J	`jnl`	Area-efficient linear regulator with ultra-fast load regulation. IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Bradley A. Bloechel, Colleen Parsons, David Finan, Shekhar Borkar
2005	J	`jnl`	Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. IEEE Micro Shekhar Borkar
2005	C	`conf`	Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
2005	Misc	`conf`	VLSI Design Challenges for Gigascale Integration. VLSI Design Shekhar Borkar
2004	—	`conf`	A low-swing single-ended L1 cache bus technique for sub-90nm technologies. ESSCIRC Peter Caputa, Mark A. Anders, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar
2004	A*	`conf`	Design and reliability challenges in nanometer technologies. DAC Shekhar Borkar, Tanay Karnik, Vivek De
2004	J	`jnl`	Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. IEEE J. Solid State Circuits Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
2004	J	`jnl`	Measurements and analysis of SER-tolerant latch in a 90-nm dual-V IEEE J. Solid State Circuits Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2004	A*	`conf`	Microarchitecture and Design Challenges for Gigascale Integration. MICRO Shekhar Borkar
2003	J	`jnl`	A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. IEEE J. Solid State Circuits Sanu Mathew, Mark A. Anders, Ram K. Krishnamurthy, Shekhar Borkar
2003	J	`jnl`	A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar
2003	J	`jnl`	A transition-encoded dynamic bus technique for high-performance interconnects. IEEE J. Solid State Circuits Mark A. Anders, Nivruti Rai, Ram K. Krishnamurthy, Shekhar Borkar
2003	—	`conf`	Bitline leakage equalization for sub-100nm caches. ESSCIRC Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson
2003	J	`jnl`	Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid State Circuits James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De
2003	A	`conf`	Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2003	C	`conf`	Exponential Challenges, Exponential Rewards - The future of Moore's Law. VLSI-SOC Shekhar Borkar
2003	J	`jnl`	Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE J. Solid State Circuits Siva G. Narendra, Ali Keshavarzi, Bradley A. Bloechel, Shekhar Borkar, Vivek De
2003	J	`jnl`	Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law. ACM Queue Shekhar Borkar
2003	J	`jnl`	Guest Editorial. IEEE J. Solid State Circuits Shekhar Borkar, Yoshinobu Nakagome
2003	—	`conf`	Low voltage sensing techniques and secondary design issues for sub-90nm caches. ESSCIRC Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar
2003	—	`conf`	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar
2003	A*	`conf`	Nanometer design: place your bets. DAC Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
2003	A*	`conf`	Parameter variations and impact on circuits and microarchitecture. DAC Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De
2002	J	`jnl`	5-GHz 32-bit integer execution core in 130-nm dual-V IEEE J. Solid State Circuits Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
2002	—	`conf`	A burn-in tolerant dynamic circuit technique. CICC Atila Alvandpour, Ram Krishnamurthy, Shekhar Borkar, A. Rahman, Clair Webb
2002	J	`jnl`	Analysis of dual-V IEEE Trans. Very Large Scale Integr. Syst. Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De
2002	A	`conf`	Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. ISLPED Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
2002	—	`conf`	High-performance and low-power challenges for sub-70 nm microprocessor circuits. CICC Ram K. Krishnamurthy, Atila Alvandpour, Vivek De, Shekhar Borkar
2002	A*	`conf`	Life is CMOS: why chase the life after? DAC George Sery, Shekhar Borkar, Vivek De
2002	A	`conf`	Sub-90nm technologies: challenges and opportunities for CAD. ICCAD Tanay Karnik, Shekhar Borkar, Vivek De
2002	A*	`conf`	Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
2001	A	`conf`	A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED Atila Alvandpour, Ram Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Borkar
2001	A	`conf`	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
2001	A	`conf`	Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. ISLPED Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De
2001	—	`conf`	Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. ACM Great Lakes Symposium on VLSI Ram Krishnamurthy, Mark A. Anders, Krishnamurthy Soumyanath, Shekhar Borkar
2001	—	`conf`	Low power design challenges for the decade (invited talk). ASP-DAC Shekhar Borkar
2001	A*	`conf`	Panel: Is Nanometer Design Under Control? DAC Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
2001	A	`conf`	Scaling of stack effect and its application for leakage reduction. ISLPED Siva G. Narendra, Vivek De, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Shekhar Borkar
2000	—	`conf`	Low power and high performance design challenges in future technologies. ACM Great Lakes Symposium on VLSI Vivek De, Shekhar Borkar
1999	J	`jnl`	Accurate on-chip interconnect evaluation: a time-domain technique. IEEE J. Solid State Circuits Krishnamurthy Soumyanath, Shekhar Borkar, Chunyan Zhou, Bradley A. Bloechel
1999	J	`jnl`	Design challenges of technology scaling. IEEE Micro Shekhar Borkar
1999	A	`conf`	Technology and design challenges for low power and high performance. ISLPED Vivek De, Shekhar Borkar
1999	A	`conf`	Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
1995	J	`jnl`	A 900 Mb/s bidirectional signaling scheme. IEEE J. Solid State Circuits Randy Mooney, Charles Dike, Shekhar Borkar
1990	A*	`conf`	Supporting Systolic and Memory Communciation in iWarp. ISCA Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb
1988	A	`conf`	Warp: an integrated solution of high-speed parallel computing. SC Shekhar Borkar, Robert Cohn, George W. Cox, Sha Gleason, Thomas R. Gross