Sheayun Lee

14 papers A* 1B 2C 2Misc 1Journal 5Unranked 3
YearRankTypeTitle / Venue / Authors
2022 B conf
Fall Detection using Biometric Information Based on Multi-Horizon Forecasting.
ICPR
Inkyung Kim, Daehee Kim, Sunyoung Kwon, Sheayun Lee, Jaekoo Lee
2018 A* conf
FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDs.
DAC
Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min
2018 J jnl
HIL: A Framework for Compositional FTL Development and Provably-Correct Crash Recovery.
ACM Trans. Storage
Jin-Yong Choi, Eyee Hyun Nam, Yoon Jae Seong, Jinhyuk Yoon, Sookwan Lee, Hongseok Kim, Jeongsu Park, Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min
2017 J jnl
P-BMS: A Bad Block Management Scheme in Parallelized Flash Memory Storage Devices.
ACM Trans. Embed. Comput. Syst.
Hongseok Kim, Eyee Hyun Nam, JiHyuck Yun, Sheayun Lee, Sang Lyul Min
2008 J jnl
A design framework for real-time embedded systems with code size and energy constraints.
ACM Trans. Embed. Comput. Syst.
Sheayun Lee, Insik Shin, Woonseok Kim, Insup Lee, Sang Lyul Min
2007 J jnl
Selective code transformation for dual instruction set processors.
ACM Trans. Embed. Comput. Syst.
Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
2006 Misc conf
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study.
CODES+ISSS
Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
2004 C conf
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.
SCOPES
Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
2003 — conf
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors.
WCET
Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
2003 C conf
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.
SCOPES
Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson
2001 — conf
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors.
LCTES/OM
Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang
2001 — conf
An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors.
OM@PLDI
Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang
1999 J jnl
Cache-Conscious Limited Preemptive Scheduling.
Real Time Syst.
Sheayun Lee, Sang Lyul Min, Chong-Sang Kim, Chang-Gun Lee, Minsuk Lee
1998 B conf
Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems.
LCTES
Sheayun Lee, Chang-Gun Lee, Minsuk Lee, Sang Lyul Min, Chong-Sang Kim