Shashidhar Thakur

13 papers A* 1A 3C 2Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2013 — conf
Knowledge in Search.
NTCIR
Shashidhar Thakur
2002 J jnl
Estimating routing congestion using probabilistic analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng
1998 J jnl
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing.
VLSI Design
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
1997 J jnl
Algorithms for an FPGA switch module routing problem with application to global routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan
1996 A* conf
Delay Minimal Decomposition of Multiplexers in Technology Mapping.
DAC
Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy
1996 J jnl
Series-parallel functions and FPGA logic module design.
ACM Trans. Design Autom. Electr. Syst.
Shashidhar Thakur, D. F. Wong
1996 J jnl
Simultaneous area and delay minimum K-LUT mapping for K-exact networks.
Integr.
Shashidhar Thakur, D. F. Wong
1996 A conf
Universal Logic Modules for Series-Parallel Functions.
FPGA
Shashidhar Thakur, D. F. Wong
1995 C conf
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing.
ISCAS
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
1995 A conf
On Designing ULM-based FPGA Logic Modules.
FPGA
Shashidhar Thakur, D. F. Wong
1995 C conf
Simultaneous area and delay minimum K-LUT mapping for K-exact networks.
ICCD
Shashidhar Thakur, D. F. Wong
1994 A conf
A new global routing algorithm for FPGAs.
ICCAD
Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
1994 — conf
Algorithms for a switch module routing problem.
EURO-DAC
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan