Sharvil Patil

18 papers C 1Journal 9Unranked 8
YearRankTypeTitle / Venue / Authors
2024 — conf
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.
ISSCC
Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury
2024 J jnl
A -90-dBFS-IM
IEEE J. Solid State Circuits
Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury
2024 J jnl
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
IEEE J. Solid State Circuits
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2023 — conf
A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs.
CICC
Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat
2023 — conf
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET.
VLSI Technology and Circuits
Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee
2022 J jnl
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mohammed Wagih Ismail, Hajime Shibata, Zhao Li, Sharvil Patil, Tony Chan Carusone
2020 — conf
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.
ISSCC
Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat, Shanthi Pavan
2019 J jnl
Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sharvil Patil, Suhas Gundu Rao, Yu Chen, Yannis P. Tsividis
2018 J jnl
Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time".
IEEE J. Solid State Circuits
Ning Guo, Yipeng Huang, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok, Simha Sethumadhavan, Yannis P. Tsividis
2017 J jnl
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD.
IEEE J. Solid State Circuits
Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan
2016 J jnl
A 3-10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC.
IEEE J. Solid State Circuits
Sharvil Patil, Alin Ratiu, Dominique Morche, Yannis P. Tsividis
2016 C conf
Digital processing of signals produced by voltage-controlled-oscillator-based continuous-time ADCs.
ISCAS
Sharvil Patil, Yannis P. Tsividis
2016 J jnl
Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time.
IEEE J. Solid State Circuits
Ning Guo, Yipeng Huang, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok, Simha Sethumadhavan, Yannis P. Tsividis
2015 — conf
A 3-10fJ/conv-step 0.0032mm
VLSIC
Sharvil Patil, Alin Ratiu, Dominique Morche, Yannis P. Tsividis
2015 — conf
Continuous-time hybrid computation with programmable nonlinearities.
ESSCIRC
Ning Guo, Yipeng Huang, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok, Simha Sethumadhavan, Yannis P. Tsividis
2015 J jnl
Derivative Level-Crossing Sampling.
IEEE Trans. Circuits Syst. II Express Briefs
Pablo Martínez-Nuevo, Sharvil Patil, Yannis P. Tsividis
2009 — conf
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers.
ARTCom
Ashutosh Mehra, Anu Gupta, Sharvil Patil, Abhishek Mehra, Subhendu Kumar Sahoo
2009 — conf
Improved Implementation of CRL and SCRL Gates for Ultra Low Power.
ARTCom
Amit Agarkhed, Sharvil Patil, Anu Gupta