Sharad Sinha - RankMe

90 papers A* 2A 12B 9Misc 3Journal 41Unranked 22

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	AP-DRL: A Synergistic Algorithm-Hardware Framework for Automatic Task Partitioning of Deep Reinforcement Learning on Versal ACAP. CoRR Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang
2025	J	`jnl`	DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning. CoRR Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang
2025	B	`conf`	Deep Learning Aided Low Latency Hybrid Beamforming with Selective Antenna Grouping. PIMRC Nikita Rathor, Neelakandan Rajamohan, Sharad Sinha
2025	A	`conf`	TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. FPGA Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang
2025	A	`conf`	UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE. DATE Yuying Zhang, Sharad Sinha, Jiang Xu, Wei Zhang
2024	J	`jnl`	AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2024	J	`jnl`	Advancing microbial diagnostics: a universal phylogeny guided computational algorithm to find unique sequences for precise microorganism detection. Briefings Bioinform. Gulshan Kumar Sharma, Rakesh Sharma, Kavita Joshi, Sameer Qureshi, Shubhita Mathur, Sharad Sinha, Samit Chatterjee, Vandana Nunia
2024	J	`jnl`	Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression. ACM Trans. Embed. Comput. Syst. Prachi Kashikar, Olivier Sentieys, Sharad Sinha
2024	—	`conf`	ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. IPDPS (Workshops) Shubhayu Das, Nanditha P. Rao, Sharad Sinha
2024	J	`jnl`	FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang
2024	A	`conf`	GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. FPGA Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang
2024	J	`jnl`	Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe). ACM Trans. Embed. Comput. Syst. Pavitra Prakash Bhade, Joseph Paturel, Olivier Sentieys, Sharad Sinha
2024	—	`conf`	Mender-FPGA: An Open Source Framework for FPGA Remote Update for ML Applications. iSES Nikita Rathor, Sharad Sinha
2024	J	`jnl`	Shielding against online harm: A survey on text analysis to prevent cyberbullying. Eng. Appl. Artif. Intell. Akanksha Mishra, Sharad Sinha, Clint Pazhayidam George
2024	J	`jnl`	Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. IEEE Trans. Very Large Scale Integr. Syst. Enlai Li, Sharad Sinha, Wei Zhang
2024	—	`conf`	VATML: Towards On Device Ventricular Arrhythmia Detection Using TinyML. iSES Vipin Gautam, Sharad Sinha, Shitala Prasad
2023	J	`jnl`	AaP-ReID: Improved Attention-Aware Person Re-identification. CoRR Vipin Gautam, Shitala Prasad, Sharad Sinha
2023	A	`conf`	Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. DATE Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang
2023	J	`jnl`	Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation. IEEE Trans. Computers Sathi Sarveswara Reddy, Sharad Sinha, Wei Zhang
2023	—	`conf`	DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. ICFPT Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha
2023	A	`conf`	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2023	J	`jnl`	HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang
2023	—	`conf`	Joint-YODNet: A Light-Weight Object Detector for UAVs to Achieve Above 100fps. CVIP (2) Vipin Gautam, Shitala Prasad, Sharad Sinha
2023	J	`jnl`	Joint-YODNet: A Light-weight Object Detector for UAVs to Achieve Above 100fps. CoRR Vipin Gautam, Shitala Prasad, Sharad Sinha
2023	J	`jnl`	Lossless Neural Network Model Compression Through Exponent Sharing. IEEE Trans. Very Large Scale Integr. Syst. Prachi Kashikar, Olivier Sentieys, Sharad Sinha
2023	—	`conf`	Message from Workshop Chairs. HiPCW Sheikh K. Ghafoor, Sushil K. Prasad, Ashish Kuvelkar, Sharad Sinha, Satish Puri
2023	Misc	`conf`	Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. FCCM Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang
2023	J	`jnl`	YOLORe-IDNet: An Efficient Multi-Camera System for Person-Tracking. CoRR Vipin Gautam, Shitala Prasad, Sharad Sinha
2023	—	`conf`	YOLORe-IDNet: An Efficient Multi-camera System for Person-Tracking. CVIP (1) Vipin Gautam, Shitala Prasad, Sharad Sinha
2022	J	`jnl`	AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. CoRR Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2022	A	`conf`	Attack Directories on ARM big.LITTLE Processors. ICCAD Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang
2022	J	`jnl`	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. CoRR Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2022	—	`conf`	Machine Learning Based Webcasting Analytics for Indian Elections - Reflections on Deployment. CVIP (2) Aditi Saxena, Sharad Sinha
2022	J	`jnl`	Workings of science: Is engineering applied science? Ubiquity Sharad Sinha
2021	J	`jnl`	A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs. Neural Process. Lett. Arish Sateesan, Sharad Sinha, Smitha K. G., A. P. Vinod
2021	A	`conf`	AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2021	—	`conf`	Compressing CNNs by Exponent Sharing in Weights using IEEE Single Precision Format. ISQED Prachi Kashikar, Sharad Sinha
2021	—	`conf`	Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters. MCSoC Pavitra Prakash Bhade, Sharad Sinha
2021	—	`conf`	Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware. AICAS Prachi Kashikar, Sharad Sinha, Ajeet Kumar Verma
2021	J	`jnl`	Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhe Lin, Sharad Sinha, Wei Zhang
2021	A*	`conf`	Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. DAC Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang
2021	—	`conf`	Variable Bit-Precision Vector Extension for RISC-V Based Processors. MCSoC Risikesh RK, Sharad Sinha, Nanditha P. Rao
2020	J	`jnl`	An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power. CoRR Zhe Lin, Sharad Sinha, Wei Zhang
2020	—	`conf`	DASH: Design Automation for Synthesis and Hardware Generation for CNN. FPT Arish Sateesan, Sharad Sinha, Smitha K. G.
2020	J	`jnl`	Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA. CoRR Zhe Lin, Wei Zhang, Sharad Sinha
2020	B	`conf`	FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
2020	J	`jnl`	FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
2020	—	`conf`	HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. ASP-DAC Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
2020	J	`jnl`	HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. CoRR Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
2020	J	`jnl`	Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. CoRR Zhe Lin, Sharad Sinha, Wei Zhang
2020	J	`jnl`	Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. ACM Trans. Reconfigurable Technol. Syst. Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
2020	J	`jnl`	Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
2020	J	`jnl`	Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. CoRR Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
2020	J	`jnl`	Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. CoRR Zhe Lin, Sharad Sinha, Wei Zhang
2020	—	`conf`	iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. ASP-DAC Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das
2019	A	`conf`	A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019	J	`jnl`	An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhe Lin, Sharad Sinha, Wei Zhang
2019	J	`jnl`	Artificial intelligence for all using R programming language. AI Matters Sharad Sinha, Clint P. George
2019	A	`conf`	Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
2019	A*	`conf`	LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019	A	`conf`	Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019	J	`jnl`	Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019	—	`conf`	Optimization of Convolutional Neural Networks on Resource Constrained Devices. ISVLSI Arish S, Sharad Sinha, Smitha K. G.
2019	—	`conf`	Smart Nation: Indoor Navigation for the Visually Impaired. ICITE Lim Boon Leng, Smitha K. G., Sharad Sinha
2019	—	`conf`	Smart Nation: Offline Public Transport Made Easy. ICITE Ang Poh Keong, K. G. Smitha, Sharad Sinha
2019	Misc	`conf`	Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. FCCM Zhe Lin, Sharad Sinha, Wei Zhang
2018	B	`conf`	A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. FPL Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
2018	Misc	`conf`	CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. FCCM Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
2018	J	`jnl`	Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
2018	J	`jnl`	Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Liang, Sharad Sinha, Wei Zhang
2018	J	`jnl`	Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. IEEE Trans. Multi Scale Comput. Syst. Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
2017	A	`conf`	A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. ICCAD Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
2017	A	`conf`	COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. ICCAD Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
2017	B	`conf`	Decision tree based hardware power monitoring for run time dynamic power management in FPGA. FPL Zhe Lin, Wei Zhang, Sharad Sinha
2017	J	`jnl`	HeteroSim: A Heterogeneous CPU-FPGA Simulator. IEEE Comput. Archit. Lett. Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
2017	B	`conf`	PAAS: A system level simulator for heterogeneous computing architectures. FPL Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang
2016	—	`conf`	Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. ARC Mohammad Tahghighi, Sharad Sinha, Wei Zhang
2016	—	`conf`	Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. ISVLSI Mohammad Tahghighi, Wei Zhang, Sharad Sinha
2016	B	`conf`	HeteroSim: A heterogeneous CPU-FPGA simulator. FPL Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
2016	J	`jnl`	Low-Power FPGA Design Using Memoization-Based Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. Sharad Sinha, Wei Zhang
2015	B	`conf`	Hierarchical library based power estimator for versatile FPGAs. FPL Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li
2015	B	`conf`	Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. FPL Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang
2014	—	`conf`	A Bit-Level Block Cipher Diffusion Analysis Test - BLDAT. FICTA (1) Dipanjan Bhowmik, Avijit Datta, Sharad Sinha
2014	J	`jnl`	Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. Int. J. Reconfigurable Comput. Sharad Sinha, Thambipillai Srikanthan
2014	J	`jnl`	Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective. ACM Trans. Design Autom. Electr. Syst. Sharad Sinha, Thambipillai Srikanthan
2014	J	`jnl`	Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs. J. Circuits Syst. Comput. Sharad Sinha, Udit Dhawan, Thambipillai Srikanthan
2014	J	`jnl`	IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance. Int. J. Reconfigurable Comput. Sharad Sinha, Thambipillai Srikanthan
2014	—	`—`	Intelligent high level synthesis for customization on reconfigurable platforms Sharad Sinha
2012	B	`conf`	Dataflow graph partitioning for high level synthesis. FPL Sharad Sinha, Thambipillai Srikanthan
2011	—	`conf`	A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. ISVLSI Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan