Sharad Malik - RankMe

291 papers A* 37A 63B 24C 9Misc 21Journal 78Unranked 48

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Compass: Navigating the Design Space of Taint Schemes for RTL Security Verification. ASPLOS (2) Yuheng Yang, Qinhan Tan, Thomas Bourgeat, Sharad Malik, Mengjia Yan
2026	J	`jnl`	SecIC3: Customizing IC3 for Hardware Security Verification. CoRR Qinhan Tan, Akash Gaonkar, Yu-Wei Fan, Aarti Gupta, Sharad Malik
2025	J	`jnl`	FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols. CoRR Yu-An Shih, Annie Lin, Aarti Gupta, Sharad Malik
2025	J	`jnl`	Hierarchical Formal Verification of Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Huaixi Lu, Yue Xing, Aarti Gupta, Sharad Malik
2025	—	`conf`	RTL Verification for Secure Speculation Using Contract Shadow Logic. ASPLOS (1) Qinhan Tan, Yuheng Yang, Thomas Bourgeat, Sharad Malik, Mengjia Yan
2024	J	`jnl`	Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface. ACM Trans. Design Autom. Electr. Syst. Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Gus Henry Smith, Thierry Tambe, Akash Gaonkar, Vishal Canumalla, Andrew Cheung, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik
2024	A	`conf`	Automatic Generation of Cycle-Accurate Timing Models from RTL for Hardware Accelerators. ICCAD Yu Zeng, Aarti Gupta, Sharad Malik
2024	A	`conf`	Automatic Verification and Identification of Partial Retention Register Sets for Low-Power Designs. ICCAD Yu-An Shih, Sharad Malik
2024	B	`conf`	Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators. ASPDAC Yi Li, Aarti Gupta, Sharad Malik
2024	J	`jnl`	Formal Verification for Secure Processors: A Guide for Computer Architects. Computer Mengjia Yan, Thomas Bourgeat, Sharad Malik
2024	J	`jnl`	RTL Verification for Secure Speculation Using Contract Shadow Logic. CoRR Qinhan Tan, Yuheng Yang, Thomas Bourgeat, Sharad Malik, Mengjia Yan
2023	J	`jnl`	CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks. ACM Trans. Design Autom. Electr. Syst. Qi Nie, Sharad Malik
2023	J	`jnl`	Combined Scheduling, Memory Allocation and Tensor Replacement for Minimizing Off-Chip Data Accesses of DNN Accelerators. CoRR Yi Li, Aarti Gupta, Sharad Malik
2023	A*	`conf`	INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. DAC Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik
2023	A*	`conf`	Security Verification of Low-Trust Architectures. CCS Qinhan Tan, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin
2023	J	`jnl`	Security Verification of Low-Trust Architectures. CoRR Qinhan Tan, Yonathan Fisseha, Shibo Chen, Lauren Biernacki, Jean-Baptiste Jeannin, Sharad Malik, Todd M. Austin
2023	J	`jnl`	SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications. ACM Trans. Design Autom. Electr. Syst. Huaixi Lu, Yue Xing, Aarti Gupta, Sharad Malik
2022	A	`conf`	Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators. DATE Yu Zeng, Aarti Gupta, Sharad Malik
2022	A	`conf`	Compositional Verification Using a Formal Component and Interface Specification. ICCAD Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik
2022	—	`conf`	Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models. ASP-DAC Yue Xing, Aarti Gupta, Sharad Malik
2022	J	`jnl`	Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface. CoRR Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Thierry Tambe, Gus Henry Smith, Akash Gaonkar, Vishal Canumalla, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik
2022	A	`conf`	Usage-Based RTL Subsetting for Hardware Accelerators. ICCAD Qinhan Tan, Aarti Gupta, Sharad Malik
2021	—	`ch.`	Conflict-Driven Clause Learning SAT Solvers. Handbook of Satisfiability João Marques-Silva, Inês Lynce, Sharad Malik
2021	A	`conf`	Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. ICCAD Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik
2021	A	`conf`	Leveraging Processor Modeling and Verification for General Hardware Modules. DATE Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik
2021	J	`jnl`	Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses. ACM J. Emerg. Technol. Comput. Syst. Lauren Biernacki, Mark Gallagher, Zhixing Xu, Misiker Tadesse Aga, Austin Harris, Shijia Wei, Mohit Tiwari, Baris Kasikci, Sharad Malik, Todd M. Austin
2021	B	`conf`	Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking. VMCAI Hongce Zhang, Aarti Gupta, Sharad Malik
2020	J	`jnl`	MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qi Nie, Sharad Malik
2020	B	`conf`	Synthesizing Environment Invariants for Modular Hardware Verification. VMCAI Hongce Zhang, Weikun Yang, Grigory Fedyukovich, Aarti Gupta, Sharad Malik
2019	—	`conf`	ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. TACAS (1) Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, Sharad Malik
2019	J	`jnl`	Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. ACM Trans. Design Autom. Electr. Syst. Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik
2019	A*	`conf`	Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. ASPLOS Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd M. Austin
2019	J	`jnl`	Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings. ACM Trans. Design Autom. Electr. Syst. Burçin Çakir, Sharad Malik
2019	C	`conf`	SpFlow: Memory-Driven Data Flow Optimization for Sparse Matrix-Matrix Multiplication. ISCAS Qi Nie, Sharad Malik
2019	J	`jnl`	Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration (long version). CoRR Pareesa Ameneh Golnari, Sharad Malik
2019	—	`conf`	Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration. ASAP Sharad Malik, Pareesa Ameneh Golnari
2018	A	`conf`	A formal instruction-level GPU model for scalable verification. ICCAD Yue Xing, Bo-Yuan Huang, Aarti Gupta, Sharad Malik
2018	A*	`conf`	Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. DAC Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik
2018	B	`conf`	ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. FMCAD Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik
2018	J	`jnl`	Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. CoRR Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, Sharad Malik
2018	—	`conf`	Lazy Self-composition for Security Verification. CAV (2) Weikun Yang, Yakir Vizel, Pramod Subramanyan, Aarti Gupta, Sharad Malik
2018	—	`conf`	MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. ASP-DAC Qi Nie, Sharad Malik
2018	—	`ch.`	Propositional SAT Solving. Handbook of Model Checking João Marques-Silva, Sharad Malik
2018	J	`jnl`	Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs. ACM Trans. Design Autom. Electr. Syst. Burçin Çakir, Sharad Malik
2018	J	`jnl`	Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pramod Subramanyan, Bo-Yuan Huang, Yakir Vizel, Aarti Gupta, Sharad Malik
2018	A	`conf`	Vulnerability-tolerant secure architectures. ICCAD Todd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari
2017	A	`conf`	Evaluating matrix representations for error-tolerant computing. DATE Pareesa Ameneh Golnari, Sharad Malik
2017	B	`conf`	IC3 - Flipping the E in ICE. VMCAI Yakir Vizel, Arie Gurfinkel, Sharon Shoham, Sharad Malik
2017	A	`conf`	Malware detection using machine learning based analysis of virtual memory access patterns. DATE Zhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik
2017	J	`jnl`	PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees. ACM J. Emerg. Technol. Comput. Syst. Pareesa Ameneh Golnari, Yavuz Yetim, Margaret Martonosi, Yakir Vizel, Sharad Malik
2017	—	`conf`	Solving Constraints over Bit-Vectors with SAT-based Model Checking. SMT Yakir Vizel, Alexander Nadel, Sharad Malik
2017	B	`conf`	Solving linear arithmetic with SAT-based model checking. FMCAD Yakir Vizel, Alexander Nadel, Sharad Malik
2017	—	`conf`	Trace-based Analysis of Memory Corruption Malware Attacks. Haifa Verification Conference Zhixing Xu, Aarti Gupta, Sharad Malik
2016	—	`conf`	Constrained Sampling and Counting: Universal Hashing Meets SAT Solving. AAAI Workshop: Beyond NP Kuldeep S. Meel, Moshe Y. Vardi, Supratik Chakraborty, Daniel J. Fremont, Sanjit A. Seshia, Dror Fried, Alexander Ivrii, Sharad Malik
2016	A*	`conf`	Invited - Specification and modeling for systems-on-chip security verification. DAC Sharad Malik, Pramod Subramanyan
2016	J	`jnl`	Model checking unbounded concurrent lists. Int. J. Softw. Tools Technol. Transf. Divjyot Sethi, Muralidhar Talupur, Sharad Malik
2016	J	`jnl`	On computing minimal independent support and its applications to sampling and counting. Constraints An Int. J. Alexander Ivrii, Sharad Malik, Kuldeep S. Meel, Moshe Y. Vardi
2016	A	`conf`	Verifying information flow properties of firmware using symbolic execution. DATE Pramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti, Jason M. Fung
2015	J	`jnl`	Boolean Satisfiability Solvers and Their Applications in Model Checking. Proc. IEEE Yakir Vizel, Georg Weissenbacher, Sharad Malik
2015	A*	`conf`	CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution. ASPLOS Yavuz Yetim, Sharad Malik, Margaret Martonosi
2015	Misc	`conf`	Completeness bounds and sequentialization for model checking of interacting firmware and hardware. CODES+ISSS Sunha Ahn, Sharad Malik, Aarti Gupta
2015	J	`jnl`	Constrained Sampling and Counting: Universal Hashing Meets SAT Solving. CoRR Kuldeep S. Meel, Moshe Y. Vardi, Supratik Chakraborty, Daniel J. Fremont, Sanjit A. Seshia, Dror Fried, Alexander Ivrii, Sharad Malik
2015	B	`conf`	Detecting Hardware Trojans: A Tale of Two Techniques. FMCAD Sharad Malik
2015	A	`conf`	Error-Tolerant Processors: Formal Specification and Verification. ICCAD Ameneh Golnari, Yakir Vizel, Sharad Malik
2015	—	`conf`	Evaluating the security of logic encryption algorithms. HOST Pramod Subramanyan, Sayak Ray, Sharad Malik
2015	—	`conf`	Fast Interpolating BMC. CAV (1) Yakir Vizel, Arie Gurfinkel, Sharad Malik
2015	A	`conf`	Hardware Trojan detection for gate-level ICs using signal correlation based clustering. DATE Burçin Çakir, Sharad Malik
2015	A	`conf`	Optimizing dynamic trace signal selection using machine learning and linear programming. DATE Charlie Shucheng Zhu, Sharad Malik
2015	B	`conf`	Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. FMCAD Pramod Subramanyan, Yakir Vizel, Sayak Ray, Sharad Malik
2014	Misc	`conf`	All-SAT Using Minimal Blocking Clauses. VLSID Yinlei Yu, Pramod Subramanyan, Nestan Tsiskaridze, Sharad Malik
2014	A	`conf`	An Adaptable Rule Placement for Software-Defined Networks. DSN Shuyuan Zhang, Franjo Ivancic, Cristian Lumezanu, Yifei Yuan, Aarti Gupta, Sharad Malik
2014	—	`conf`	An assertion language for debugging SDN applications. HotSDN Ryan Beckett, Xuan Kelvin Zou, Shuyuan Zhang, Sharad Malik, Jennifer Rexford, David Walker
2014	Misc	`conf`	Automated firmware testing using firmware-hardware interaction patterns. CODES+ISSS Sunha Ahn, Sharad Malik
2014	—	`ch.`	Boolean Satisfiability: Solvers and Extensions. Software Systems Safety Georg Weissenbacher, Pramod Subramanyan, Sharad Malik
2014	—	`conf`	Effective abstraction for response proof of communication fabrics. NOCS Sayak Ray, Sharad Malik
2014	B	`conf`	In-Band Update for Network Routing Policy Migration. ICNP Shuyuan Zhang, Sharad Malik, Sanjai Narain, Laurent Vanbever
2014	—	`conf`	Reduction of Resolution Refutations and Interpolants via Subsumption. Haifa Verification Conference Roderick Bloem, Sharad Malik, Matthias Schlaipfer, Georg Weissenbacher
2014	J	`jnl`	Reverse Engineering Digital Circuits Using Structural and Functional Analyses. IEEE Trans. Emerg. Top. Comput. Pramod Subramanyan, Nestan Tsiskaridze, Wenchao Li, Adrià Gascón, Wei Yang Tan, Ashish Tiwari, Natarajan Shankar, Sanjit A. Seshia, Sharad Malik
2014	A	`conf`	Silicon fault diagnosis using sequence interpolation with backbones. ICCAD Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik
2014	B	`conf`	Template-based circuit understanding. FMCAD Adrià Gascón, Pramod Subramanyan, Bruno Dutertre, Ashish Tiwari, Dejan Jovanovic, Sharad Malik
2014	B	`conf`	Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. ATVA Divjyot Sethi, Muralidhar Talupur, Sharad Malik
2014	J	`jnl`	Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. CoRR Divjyot Sethi, Muralidhar Talupur, Sharad Malik
2013	B	`conf`	Abstractions for model checking SDN controllers. FMCAD Divjyot Sethi, Srinivas Narayana, Sharad Malik
2013	A	`conf`	Extracting useful computation from error-prone processors for streaming applications. DATE Yavuz Yetim, Margaret Martonosi, Sharad Malik
2013	—	`conf`	Model Checking Unbounded Concurrent Lists. SPIN Divjyot Sethi, Muralidhar Talupur, Sharad Malik
2013	—	`conf`	Modeling Firmware as Service Functions and Its Application to Test Generation. Haifa Verification Conference Sunha Ahn, Sharad Malik
2013	A	`conf`	Reverse engineering digital circuits using functional analysis. DATE Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea, Sharad Malik
2013	B	`conf`	SAT Based Verification of Network Data Planes. ATVA Shuyuan Zhang, Sharad Malik
2013	—	`conf`	WordRev: Finding word-level structures in a sea of bit-level gates. HOST Wenchao Li, Adrià Gascón, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari, Sharad Malik, Natarajan Shankar, Sanjit A. Seshia
2012	—	`ch.`	Boolean Satisfiability Solvers: Techniques and Extensions. Software Safety and Security Georg Weissenbacher, Sharad Malik
2012	—	`conf`	Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation. Haifa Verification Conference Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik
2012	—	`conf`	EPROF: An energy/performance/reliability optimization framework for streaming applications. ASP-DAC Yavuz Yetim, Sharad Malik, Margaret Martonosi
2012	B	`conf`	Efficient predictive analysis for detecting nondeterminism in multi-threaded programs. FMCAD Arnab Sinha, Sharad Malik, Aarti Gupta
2012	B	`conf`	Parallel Assertions for Architectures with Weak Memory Models. ATVA Daniel Schwartz-Narbonne, Georg Weissenbacher, Sharad Malik
2012	—	`conf`	Parameterized Model Checking of Fine Grained Concurrency. SPIN Divjyot Sethi, Muralidhar Talupur, Daniel Schwartz-Narbonne, Sharad Malik
2012	A*	`conf`	Specification and synthesis of hardware checkpointing and rollback mechanisms. DAC Carven Chan, Daniel Schwartz-Narbonne, Divjyot Sethi, Sharad Malik
2012	B	`conf`	Verification and synthesis of firewalls using SAT and QBF. ICNP Shuyuan Zhang, Abdulrahman Mahmoud, Sharad Malik, Sanjai Narain
2012	B	`conf`	Verification of Computer Switching Networks: An Overview. ATVA Shuyuan Zhang, Sharad Malik, Rick McGeer
2012	A	`conf`	Wolverine: Battling Bugs with Interpolants - (Competition Contribution). TACAS Georg Weissenbacher, Daniel Kroening, Sharad Malik
2012	A*	`conf`	passert: A Tool for Debugging Parallel Programs. CAV Daniel Schwartz-Narbonne, Feng Liu, David I. August, Sharad Malik
2011	C	`conf`	Parallel assertions for debugging parallel programs. MEMOCODE Daniel Schwartz-Narbonne, Feng Liu, Tarun Pondicherry, David I. August, Sharad Malik
2011	B	`conf`	Post-silicon fault localisation using maximum satisfiability and backbones. FMCAD Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik
2011	—	`conf`	Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search. Haifa Verification Conference Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta
2011	C	`conf`	Predictive analysis for detecting serializability violations through Trace Segmentation. MEMOCODE Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta
2011	B	`conf`	Runtime Verification: A Computer Architecture Perspective. RV Sharad Malik
2011	—	`conf`	SAT-based techniques for determining backbones for post-silicon fault localisation. HLDVT Charlie Shucheng Zhu, Georg Weissenbacher, Divjyot Sethi, Sharad Malik
2011	J	`jnl`	Specification and encoding of transaction interaction properties. Formal Methods Syst. Des. Divjyot Sethi, Yogesh S. Mahajan, Sharad Malik
2011	—	`conf`	Towards Eliminating Configuration Errors in Cyber Infrastructure. SafeConfig Sanjai Narain, Sharad Malik, Ehab Al-Shaer
2010	A	`conf`	Runtime checking of serializability in software transactional memory. IPDPS Arnab Sinha, Sharad Malik
2010	—	`conf`	Utility of transaction-level hardware models in refinement checking. HLDVT Yogesh S. Mahajan, Sharad Malik
2009	J	`jnl`	Boolean satisfiability from theoretical hardness to practical success. Commun. ACM Sharad Malik, Lintao Zhang
2009	—	`ch.`	Conflict-Driven Clause Learning SAT Solvers. Handbook of Satisfiability João Marques-Silva, Inês Lynce, Sharad Malik
2009	J	`jnl`	Preface. Formal Methods Syst. Des. Aarti Gupta, Sharad Malik
2009	Misc	`conf`	Supporting RTL flow compatibility in a microarchitecture-level design framework. CODES+ISSS Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik
2008	J	`jnl`	Challenges and Solutions for Late- and Post-Silicon Design. IEEE Des. Test Comput. Jan M. Rabaey, Sharad Malik
2008	A*	`ed.`	Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings CAV Aarti Gupta, Sharad Malik
2008	J	`jnl`	Declarative Infrastructure Configuration Synthesis and Debugging. J. Netw. Syst. Manag. Sanjai Narain, Gary Levin, Sharad Malik, Vikram Kaul
2008	Misc	`conf`	Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. VLSI Design Yinlei Yu, Cameron Brien, Sharad Malik
2008	A	`conf`	Hardware Verification: Techniques, Methodology and Solutions. TACAS Sharad Malik
2008	—	`conf`	Runtime Validation of Transactional Memory Systems. ISQED Kaiyu Chen, Sharad Malik, Priyadarsan Patra
2008	A*	`conf`	Runtime validation of memory ordering using constraint graph checking. HPCA Kaiyu Chen, Sharad Malik, Priyadarsan Patra
2007	—	`ch.`	A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook, 2nd ed. Subramanian Rajagopalan, Sharad Malik
2007	J	`jnl`	A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. ACM Trans. Design Autom. Electr. Syst. Xinping Zhu, Sharad Malik
2007	—	`ch.`	Architecture Description Languages for Retargetable Compilation. The Compiler Design Handbook, 2nd ed. Wei Qin, Sharad Malik
2007	B	`conf`	Automating Hazard Checking in Transaction-Level Microarchitecture Models. FMCAD Yogesh S. Mahajan, Sharad Malik
2007	Misc	`conf`	Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. VLSI Design Zhaohui Fu, Sharad Malik
2007	C	`conf`	Verification Driven Formal Architecture and Microarchitecture Modeling. MEMOCODE Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin
2006	C	`conf`	Dependable Multithreaded Processing Using Runtime Validation. PRDC Kaiyu Chen, Sharad Malik
2006	A	`conf`	Lemma Learning in SMT on Linear Constraints. SAT Yinlei Yu, Sharad Malik
2006	J	`jnl`	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. IEEE Trans. Very Large Scale Integr. Syst. Xinping Zhu, Wei Qin, Sharad Malik
2006	A	`conf`	On Solving the Partial MAX-SAT Problem. SAT Zhaohui Fu, Sharad Malik
2006	A	`conf`	Solving Quantified Boolean Formulas with Circuit Observability Don't Cares. SAT Daijue Tang, Sharad Malik
2006	A	`conf`	Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. ICCAD Zhaohui Fu, Sharad Malik
2006	J	`jnl`	The Liberty Simulation Environment: A deliberate approach to high-level system modeling. ACM Trans. Comput. Syst. Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, Sharad Malik, David I. August
2006	B	`conf`	Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis. FMCAD Cameron Brien, Sharad Malik
2005	—	`conf`	A Case for Runtime Validation of Hardware. Haifa Verification Conference Sharad Malik
2005	—	`conf`	A Study of Architecture Description Languages from a Model-based Perspective. MTV Wei Qin, Sharad Malik
2005	A	`conf`	A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. DATE Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
2005	J	`jnl`	Achieving Structural and Composable Modeling of Complex Systems. Int. J. Parallel Program. David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai, Manish Vachharajani, Paul Willmann
2005	A	`conf`	Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. ISLPED Fen Xie, Margaret Martonosi, Sharad Malik
2005	A	`conf`	Complementary use of runtime validation and model checking. ICCAD Ali Alphan Bayazit, Sharad Malik
2005	A	`conf`	Considering Circuit Observability Don't Cares in CNF Satisfiability. DATE Zhaohui Fu, Yinlei Yu, Sharad Malik
2005	Misc	`conf`	Efficient behavior-driven runtime dynamic voltage scaling policies. CODES+ISSS Fen Xie, Margaret Martonosi, Sharad Malik
2005	A*	`conf`	Symmetry Reduction in SAT-Based Model Checking. CAV Daijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip
2005	—	`conf`	Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice. ASP-DAC Yinlei Yu, Sharad Malik
2004	A	`conf`	A Comparative Study of 2QBF Algorithms. SAT Darsh Ranjan, Daijue Tang, Sharad Malik
2004	B	`conf`	A formal concurrency model based architecture description language for synthesis of software development tools. LCTES Wei Qin, Subramanian Rajagopalan, Sharad Malik
2004	—	`conf`	Achieving Structural and Composable Modeling of Complex Systems. IPDPS Next Generation Software Program - NSFNGS - PI Workshop David I. August, Sharad Malik, Li-Shiuan Peh, Vijay S. Pai
2004	—	`conf`	Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. SAT (Selected Papers Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik
2004	A	`conf`	Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. SAT Daijue Tang, Yinlei Yu, Darsh Ranjan, Sharad Malik
2004	Misc	`conf`	Facilitating reuse in hardware models with enhanced type inference. CODES+ISSS Manish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August
2004	J	`jnl`	Guest Editors' Introduction: Exploring Synergies for Design Verification. IEEE Des. Test Comput. Carl Pixley, Sharad Malik
2004	J	`jnl`	Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. ACM Trans. Archit. Code Optim. Fen Xie, Margaret Martonosi, Sharad Malik
2004	Misc	`conf`	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. CODES+ISSS Xinping Zhu, Wei Qin, Sharad Malik
2004	A*	`ed.`	Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004 DAC Sharad Malik, Limor Fix, Andrew B. Kahng
2004	J	`jnl`	The design of dynamically reconfigurable datapath coprocessors. ACM Trans. Embed. Comput. Syst. Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo
2004	A	`conf`	Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. DATE Xinping Zhu, Sharad Malik
2004	—	`conf`	Zchaff2004: An Efficient SAT Solver. SAT (Selected Papers Yogesh S. Mahajan, Zhaohui Fu, Sharad Malik
2003	J	`jnl`	A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. IEEE Micro Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
2003	A*	`conf`	Automated synthesis of efficient binary decoders for retargetable software toolkits. DAC Wei Qin, Sharad Malik
2003	A	`conf`	Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms. SAT Lintao Zhang, Sharad Malik
2003	A*	`conf`	Compile-time dynamic voltage scaling settings: opportunities and limits. PLDI Fen Xie, Margaret Martonosi, Sharad Malik
2003	A	`conf`	Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. DATE Wei Qin, Sharad Malik
2003	—	`ch.`	Modeling and Integration of Peripheral Devices in Embedded Systems. Embedded Software for SoC Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi
2003	A	`conf`	Modeling and Integration of Peripheral Devices in Embedded Systems. DATE Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi
2003	A*	`conf`	Power-driven Design of Router Microarchitectures in On-chip Networks. MICRO Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
2003	Misc	`conf`	Synthesizing operating system based device drivers in embedded systems. CODES+ISSS Shaojie Wang, Sharad Malik
2003	A	`conf`	Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. DATE Lintao Zhang, Sharad Malik
2002	—	`conf`	A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. Hot Interconnects Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
2002	A	`conf`	A hierarchical modeling framework for on-chip communication architectures. ICCAD Xinping Zhu, Sharad Malik
2002	—	`ch.`	Architecture Description Languages for Retargetable Compilation. The Compiler Design Handbook Wei Qin, Sharad Malik
2002	A*	`conf`	Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik
2002	A	`conf`	Conflict driven learning in a quantified Boolean Satisfiability solver. ICCAD Lintao Zhang, Sharad Malik
2002	—	`conf`	Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. ISSS Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano
2002	Misc	`conf`	Design Tools for Application Specific Embedded Processors. EMSOFT Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh
2002	J	`jnl`	Developing Architectural Platforms: A Disciplined Approach. IEEE Des. Test Comput. Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik
2002	A*	`conf`	Exploiting operation level parallelism through dynamically reconfigurable datapaths. DAC Zhining Huang, Sharad Malik
2002	C	`conf`	From ASIC to ASIP: The Next Design Discontinuity. ICCD Kurt Keutzer, Sharad Malik, A. Richard Newton
2002	J	`jnl`	Limits of Using Signatures for Permutation Independent Boolean Comparison. Formal Methods Syst. Des. Janett Mohnke, Paul Molitor, Sharad Malik
2002	A*	`conf`	Orion: a power-performance simulator for interconnection networks. MICRO Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik
2002	—	`ch.`	Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook Subramanian Rajagopalan, Sharad Malik
2002	A	`conf`	The Quest for Efficient Boolean Satisfiability Solvers. CADE Lintao Zhang, Sharad Malik
2002	A*	`conf`	The Quest for Efficient Boolean Satisfiability Solvers. CAV Lintao Zhang, Sharad Malik
2002	A	`conf`	Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation. CP Lintao Zhang, Sharad Malik
2002	A*	`conf`	Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? DAC Gary Smith, Daya Nadamuni, Sharad Malik, Rick Chapman, John Fogelin, Kurt Keutzer, Grant Martin, Brian Bailey
2001	J	`jnl`	A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
2001	—	`conf`	Accelerating boolean satisfiability through application specific processing. ISSS Ying Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan
2001	A*	`conf`	Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. DAC Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
2001	J	`jnl`	Application of BDDs in Boolean matching techniques for formal logic combinational verification. Int. J. Softw. Tools Technol. Transf. Janett Mohnke, Paul Molitor, Sharad Malik
2001	A*	`conf`	Chaff: Engineering an Efficient SAT Solver. DAC Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik
2001	A	`conf`	Efficient Conflict Driven Learning in Boolean Satisfiability Solver. ICCAD Lintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik
2001	Misc	`conf`	Embedded Software Implementation Tools for Fully Programmable Application Specific Systems. EMSOFT Sharad Malik
2001	A	`conf`	Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. DATE Zhining Huang, Sharad Malik
2001	C	`conf`	Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. ICCD Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan
2001	B	`conf`	Optimal Live Range Merge for Address Register Allocation in Embedded Programs. CC Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik
2001	A	`conf`	Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik
2001	—	`conf`	Retargetable static timing analysis for embedded software. ISSS Kaiyu Chen, Sharad Malik, David I. August
2001	J	`jnl`	Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. Pranav Ashar, Aarti Gupta, Sharad Malik
2000	A	`conf`	Automated cache optimizations using CME driven diagnosis. ICS Somnath Ghosh, Margaret Martonosi, Sharad Malik
2000	A*	`conf`	Embedded systems education (panel abstract). DAC Sharad Malik, D. K. Arvind, Edward A. Lee, Phil Koopman, Alberto L. Sangiovanni-Vincentelli, Wayne H. Wolf
2000	J	`jnl`	Exact memory size estimation for array computations. IEEE Trans. Very Large Scale Integr. Syst. Ying Zhao, Sharad Malik
2000	Misc	`conf`	Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. CASES Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik
2000	A	`conf`	Incremental CAD. ICCAD Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh
2000	Misc	`conf`	Processor Evaluation in an Embedded Systems Design Environment. VLSI Design T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik
2000	J	`jnl`	Simultaneous reference allocation in code generation for dual data memory bank ASIPs. ACM Trans. Design Autom. Electr. Syst. Ashok Sudarsanam, Sharad Malik
1999	J	`jnl`	A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. Des. Autom. Embed. Syst. Ashok Sudarsanam, Sharad Malik, Masahiro Fujita
1999	Misc	`conf`	CAD Techniques for Embedded System Design. VLSI Design Srinivas Devadas, Sharad Malik, José Monteiro, Luciano Lavagno
1999	J	`jnl`	Cache miss equations: a compiler framework for analyzing and tuning memory behavior. ACM Trans. Program. Lang. Syst. Somnath Ghosh, Margaret Martonosi, Sharad Malik
1999	—	`conf`	Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
1999	J	`jnl`	Establishing latch correspondence for sequential circuits using distinguishing signatures. Integr. Janett Mohnke, Paul Molitor, Sharad Malik
1999	A*	`conf`	Exact Memory Size Estimation for Array Computations without Loop Unrolling. DAC Ying Zhao, Sharad Malik
1999	—	`conf`	Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME Aarti Gupta, Pranav Ashar, Sharad Malik
1999	J	`jnl`	Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis. Des. Autom. Embed. Syst. Ashok Sudarsanam, Sharad Malik, Steven W. K. Tjiang, Stan Y. Liao
1999	—	`book`	Performance analysis of real-time embedded software. Yau-Tsun Steven Li, Sharad Malik
1999	J	`jnl`	Performance estimation of embedded software with instruction cache modeling. ACM Trans. Design Autom. Electr. Syst. Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
1999	J	`jnl`	Using configurable computing to accelerate Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
1998	Misc	`conf`	Accelerating Boolean Satisfiability with Configurable Hardware. FCCM Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
1998	J	`jnl`	Code generation for fixed-point DSPs. ACM Trans. Design Autom. Electr. Syst. Guido Araujo, Sharad Malik
1998	J	`jnl`	Guarded evaluation: pushing power management to logic synthesis/design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vivek Tiwari, Sharad Malik, Pranav Ashar
1998	A*	`conf`	Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity. ASPLOS Somnath Ghosh, Margaret Martonosi, Sharad Malik
1998	B	`conf`	Solving Boolean Satisfiability with Dynamic Hardware Configurations. FPL Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik
1998	A*	`conf`	Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. DAC Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi
1997	A	`conf`	Cache Miss Equations: An Analytical Representation of Cache Misses. International Conference on Supercomputing Somnath Ghosh, Margaret Martonosi, Sharad Malik
1997	—	`conf`	Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software. Euro-Par Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
1997	J	`jnl`	Delay abstraction in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Noriya Kobayashi, Sharad Malik
1997	Misc	`conf`	Dynamic Power Management for Microprocessors: A Case Study. VLSI Design Vivek Tiwari, Ryan Donnelly, Sharad Malik, Ricardo Gonzalez
1997	Misc	`conf`	Optimization of embedded DSP programs using post-pass data-flow analysis. ICASSP Ashok Sudarsanam, Sharad Malik, Steven W. K. Tjiang, Stan Y. Liao
1997	J	`jnl`	Performance analysis of embedded software using implicit path enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yau-Tsun Steven Li, Sharad Malik
1997	J	`jnl`	Power analysis and minimization techniques for embedded DSP software. IEEE Trans. Very Large Scale Integr. Syst. Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
1997	A*	`conf`	Static Timing Analysis of Embedded Software. DAC Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li
1997	A*	`conf`	Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC Aarti Gupta, Sharad Malik, Pranav Ashar
1996	A	`conf`	Cache modeling for real-time software: beyond direct mapped instruction caches. RTSS Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
1996	Misc	`conf`	Instruction Level Power Analysis and Optimization of Software. VLSI Design Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
1996	—	`conf`	Instruction Set Design and Optimizations for Address Computation in DSP Architectures. ISSS Guido Araujo, Ashok Sudarsanam, Sharad Malik
1996	J	`jnl`	Instruction level power analysis and optimization of software. J. VLSI Signal Process. Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
1996	Misc	`conf`	Register Transfer Level Synthesis: From Theory to Practice. VLSI Design Kurt Keutzer, Sharad Malik
1996	J	`jnl`	Technology mapping for low power in logic synthesis. Integr. Vivek Tiwari, Pranav Ashar, Sharad Malik
1996	A	`conf`	The case for retiming with explicit reset circuitry. ICCAD Vigyan Singhal, Sharad Malik, Robert K. Brayton
1996	A*	`conf`	Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. DAC Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
1996	A	`conf`	Using complete-1-distinguishability for FSM equivalence checking. ICCAD Pranav Ashar, Aarti Gupta, Sharad Malik
1995	A*	`conf`	A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. DAC Srinivas Devadas, Sharad Malik
1995	—	`conf`	Delay abstraction in combinational logic circuits. ASP-DAC Noriya Kobayashi, Sharad Malik
1995	A	`conf`	Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. RTSS Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
1995	J	`jnl`	Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Sujit Dey, Sharad Malik
1995	A	`conf`	Fast functional simulation using branching programs. ICCAD Pranav Ashar, Sharad Malik
1995	J	`jnl`	Functional timing analysis using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pranav Ashar, Sharad Malik
1995	—	`conf`	Guarded evaluation: pushing power management to logic synthesis/design. ISLPD Vivek Tiwari, Sharad Malik, Pranav Ashar
1995	—	`conf`	Limits of using signatures for permutation independent Boolean comparison. ASP-DAC Janett Mohnke, Paul Molitor, Sharad Malik
1995	A	`conf`	Memory bank and register allocation in software synthesis for ASIPs. ICCAD Ashok Sudarsanam, Sharad Malik
1995	J	`jnl`	Multisensor Integration for Underwater Scene Classification. Appl. Intell. N. Nandhakumar, Sharad Malik
1995	—	`conf`	Optimal code generation for embedded memory non-homogeneous register architectures. ISSS Guido Araujo, Sharad Malik
1995	A*	`conf`	Performance Analysis of Embedded Software Using Implicit Path Enumeration. DAC Yau-Tsun Steven Li, Sharad Malik
1995	—	`conf`	Performance Analysis of Embedded Software Using Implicit Path Enumeration. Workshop on Languages, Compilers, & Tools for Real-Time Systems Yau-Tsun Steven Li, Sharad Malik
1995	A	`conf`	Performance estimation of embedded software with instruction cache modeling. ICCAD Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe
1995	—	`conf`	Power analysis and low-power scheduling techniques for embedded DSP software. ISSS Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
1995	—	`conf`	Prediction of interconnect delay in logic synthesis. ED&TC Horng-Fei Jyu, Sharad Malik
1995	Misc	`conf`	Test generation for cyclic combinational circuits. VLSI Design Anand Raghunathan, Pranav Ashar, Sharad Malik
1995	J	`jnl`	Test generation for cyclic combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anand Raghunathan, Pranav Ashar, Sharad Malik
1994	J	`jnl`	Analysis of cyclic combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad Malik
1994	J	`jnl`	Certified timing verification and the transition delay of a logic circuit. IEEE Trans. Very Large Scale Integr. Syst. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1994	—	`conf`	Challenges in code generation for embedded processors. Code Generation for Embedded Processors Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang
1994	J	`jnl`	Editorial. J. VLSI Signal Process. Teresa H. Meng, Sharad Malik
1994	J	`jnl`	Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1994	A*	`conf`	Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. DAC Pranav Ashar, Sharad Malik
1994	A	`conf`	Power analysis of embedded software: a first step towards software power minimization. ICCAD Vivek Tiwari, Sharad Malik, Andrew Wolfe
1994	J	`jnl`	Power analysis of embedded software: a first step towards software power minimization. IEEE Trans. Very Large Scale Integr. Syst. Vivek Tiwari, Sharad Malik, Andrew Wolfe
1994	A*	`conf`	Statistical Delay Modeling in Logic Design and Synthesis. DAC Horng-Fei Jyu, Sharad Malik
1994	J	`jnl`	Verification of asynchronous interface circuits with bounded wire delays. J. VLSI Signal Process. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1993	J	`jnl`	A synthesis-based test generation and compaction algorithm for multifaults. J. Electron. Test. Srinivas Devadas, Kurt Keutzer, Sharad Malik
1993	A	`conf`	Analysis of cyclic combinational circuits. ICCAD Sharad Malik
1993	J	`jnl`	Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1993	J	`jnl`	Computation of floating mode delay in combinational circuits: theory and algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srinivas Devadas, Kurt Keutzer, Sharad Malik
1993	J	`jnl`	Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	J	`jnl`	Permutation and phase independent Boolean comparison. Integr. Janett Mohnke, Sharad Malik
1993	C	`conf`	Statistical Timing Optimization of Combinatorial Logic Circuits. ICCD Horng-Fei Jyu, Sharad Malik
1993	J	`jnl`	Statistical timing analysis of combinational logic circuits. IEEE Trans. Very Large Scale Integr. Syst. Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer
1993	A*	`conf`	Technology Mapping for Lower Power. DAC Vivek Tiwari, Pranav Ashar, Sharad Malik
1992	A*	`conf`	Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1992	A	`conf`	Exploiting multi-cycle false paths in the performance optimization of sequential circuits. ICCAD Pranav Ashar, Sujit Dey, Sharad Malik
1992	C	`conf`	Statistical Timing Analysis of Combinational Circuits. ICCD Srinivas Devadas, Horng-Fei Jyu, Kurt Keutzer, Sharad Malik
1992	J	`jnl`	Symbolic minimization of multilevel logic and the input encoding problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A	`conf`	Verification of asynchronous interface circuits with bounded wire delays. ICCAD Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1991	A*	`conf`	A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults. DAC Srinivas Devadas, Kurt Keutzer, Sharad Malik
1991	A	`conf`	Delay Computation in Combinational Logic Circuits: Theory and Algorithms. ICCAD Srinivas Devadas, Kurt Keutzer, Sharad Malik
1991	J	`jnl`	Is redundancy necessary to reduce delay? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kurt Keutzer, Sharad Malik, Alexander Saldanha
1991	J	`jnl`	Retiming and resynthesis: optimizing sequential networks with combinational techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A	`conf`	Algorithms for Discrete Function Manipulation. ICCAD Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton
1990	A*	`conf`	Is Redundancy Necessary to Reduce Delay. DAC Kurt Keutzer, Sharad Malik, Alexander Saldanha
1990	A	`conf`	MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. ICCAD Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A	`conf`	Performance Optimization of Pipelined Circuits. ICCAD Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1988	A	`conf`	Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli