Shaolan Li - RankMe

53 papers A* 2A 2C 1Journal 25Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 32-Channel 85.4 dB SNDR Time-Multiplexed Neural Recording Front-End Achieving Within-Conversion Artifact Recovery. IEEE J. Solid State Circuits Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Kevin Patino-Sosa, Philip Anschutz, Amanda L. Jacob, Keshav Ramachandra, Samuel J. Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe
2026	J	`jnl`	A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression. IEEE J. Solid State Circuits Chenyang Li, Tzu-Han Wang, Dong Suk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh S. Sathe, Shaolan Li
2026	J	`jnl`	A 95.9-dB SNDR 10-kHz BW Third-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer. IEEE J. Solid State Circuits Ken Li, Wei-En Lee, Xitie Zhang, Tian Xie, Tzu-Han Wang, Visvesh S. Sathe, Shaolan Li
2025	J	`jnl`	A 1.11 mm IEEE Trans. Biomed. Circuits Syst. Xitie Zhang, Evren F. Arkan, Coskun Tekes, M. Sait Kilinc, Tzu-Han Wang, F. Levent Degertekin, Shaolan Li
2025	—	`conf`	A 32-Channel 85.4dB SNDR Time-multiplexed Neural Recording Frontend Achieving Within-Conversion Artifact Recovery. CICC Arindam Mandal, Chi-Hsiang Huang, Julian Arenas, Wei-En Lee, Philip Anschutz, Amanda L. Jacob, Keshav Ramachandra, Samuel J. Sober, Muhannad S. Bakir, Shaolan Li, Visvesh S. Sathe
2025	—	`conf`	A 50-kHz BW 92.1-dB SNDR Incremental ADC Using a Back-End Sampling Two-Step NS-SAR Architecture with Concurrent Gain-Error + Noise Suppression. CICC Tzu-Han Wang, Chenyang Li, Dong Suk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh Sathe, Shaolan Li
2025	—	`conf`	A 95.9-dB SNDR 10-kHz BW 3rd-Order VCO-Based CT ΔΣ Modulator Using a Phase-Time Two-Step Quantizer. CICC Ken Li, Wei-En Lee, Xitie Zhang, Tian Xie, Tzu-Han Wang, Visvesh Sathe, Shaolan Li
2025	J	`jnl`	From Systematic to Intelligent: Assessing AI-Empowered Optimization Techniques for Analog Building Block Sizing. IEEE Access Yijia Hao, Miguel Gandara, Srinjoy Mitra, Maarten Strackx, Sandy Cochran, Francisco V. Fernández, Shaolan Li, Bo Liu
2025	J	`jnl`	Guest Editorial 2024 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Taiyun Chi, Yoonmyung Lee, Shaolan Li
2025	J	`jnl`	VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator. IEEE Trans. Very Large Scale Integr. Syst. Ken Li, Tian Xie, Tzu-Han Wang, Shaolan Li
2024	—	`conf`	An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping. CICC Tian Xie, Ken Li, Tzu-Han Wang, Wei-En Lee, Engin Esen, Dong Suk Kang, Shaolan Li
2024	J	`jnl`	Guest Editorial 2023 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits Yan Lu, Shaolan Li
2023	—	`conf`	A 1.11 mm ESSCIRC Xitie Zhang, Evren F. Arkan, Coskun Tekes, Tzuhan Wang, F. Levent Degertekin, Shaolan Li
2023	—	`conf`	A Systematic and Innovative Six-in-One Evaluation Framework to Drive the Development of Future Hidden Champions. HCI (26) Dayou Wu, Guochao Peng, Yiwan Ai, Huan Li, Shaolan Li, Yating Peng
2023	—	`conf`	Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator. BioCAS Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu
2022	J	`jnl`	An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique. IEEE J. Solid State Circuits Tian Xie, Tzu-Han Wang, Zhe Liu, Shaolan Li
2022	—	`conf`	An 84dB-SNDR Low-OSR 4 ISSCC Tzuhan Wang, Tian Xie, Zhe Liu, Shaolan Li
2022	J	`jnl`	Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. IEEE Trans. Circuits Syst. II Express Briefs Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2022	J	`jnl`	Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun
2022	J	`jnl`	Nonvolatile Capacitive Crossbar Array for In-Memory Computing. Adv. Intell. Syst. Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu
2021	—	`conf`	27.3 A 13.8-ENOB 0.4pF-CIN 3 ISSCC Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Shaolan Li
2021	J	`jnl`	A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation. IEEE J. Solid State Circuits Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li
2021	—	`conf`	An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. CICC Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun
2021	—	`conf`	Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. IMW Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu
2021	J	`jnl`	MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan
2020	J	`jnl`	A 0.025-mm IEEE J. Solid State Circuits Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2020	J	`jnl`	A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun
2020	J	`jnl`	A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun
2020	—	`conf`	A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier. MWSCAS Shaolan Li
2020	J	`jnl`	An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun
2020	J	`jnl`	An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits Shaolan Li, David Z. Pan, Nan Sun
2019	—	`conf`	A 0.01mm ISSCC Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun
2019	—	`conf`	A 0.025-mm CICC Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun
2019	J	`jnl`	A 0.029-mm IEEE J. Solid State Circuits Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun
2019	—	`conf`	A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun
2019	—	`conf`	A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, Nan Sun
2019	—	`conf`	A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC Shaolan Li, Biying Xu, David Z. Pan, Nan Sun
2019	J	`jnl`	A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu
2019	J	`jnl`	Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. IEICE Trans. Electron. Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun
2019	—	`conf`	Device Layer-Aware Analytical Placement for Analog Circuits. ISPD Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan
2019	J	`jnl`	Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun
2019	A	`conf`	GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A	`conf`	MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan
2019	A*	`conf`	WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan
2018	—	`conf`	A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2 VLSI Circuits Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun
2018	—	`conf`	A 13-ENOB 2 ISSCC Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun
2018	J	`jnl`	A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun
2018	—	`conf`	A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun
2018	C	`conf`	Low-power Scaling-friendly Ring Oscillator based ΔΣ ADC. ISCAS Arindam Sanyal, Shaolan Li, Nan Sun
2017	J	`jnl`	A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS. IEEE J. Solid State Circuits Shaolan Li, Abhishek Mukherjee, Nan Sun
2017	A*	`conf`	A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. DAC Biying Xu, Shaolan Li, Nan Sun, David Z. Pan
2017	—	`conf`	Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. ISPD Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan
2016	—	`conf`	A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS. ESSCIRC Shaolan Li, Nan Sun