Shao-Yun Fang - RankMe

88 papers A* 13A 17Journal 30Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Optimal Mixed-Cell-Height Detailed Placement with Discrete Spacing Costs. ACM Trans. Design Autom. Electr. Syst. Da-Wei Huang, Ying-Jie Jiang, Shao-Yun Fang
2026	—	`conf`	Technology-Aware 3D Placement with ILP-Based Region Planning for Soft Modules. ISPD Cheng-Xun Song, Minh Anh Phan, Sheng-Tan Huang, Shao-Yun Fang, Tung-Chieh Chen, Kai-Shun Hu, Cindy Chin-Fang Shen
2025	A	`conf`	(Invited Paper) Overview of 2025 CAD Contest at ICCAD. ICCAD Chung-Kuan Cheng, Shao-Yun Fang, Yi-Yu Liu, Tsun-Ming Tseng
2025	A	`conf`	(Invited) Generalized GPU-Accelerated Dynamic Programming with Application to Mixed-Cell-Height Detailed Placement. ICCAD Da-Wei Huang, Shao-Yun Fang, Wen-Hao Liu
2025	—	`conf`	CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip. ASP-DAC Yan-Ting Chen, Zhidan Zheng, Shao-Yun Fang, Tsun-Ming Tseng, Ulf Schlichtmann
2025	J	`jnl`	Exploring "Many in Few" and "Few in Many" Properties in Long-Tailed, Highly-Imbalanced IC Defect Classification. CoRR Hao-Chiang Shao, Chun-Hao Chang, Yu-Hsien Lin, Chia-Wen Lin, Shao-Yun Fang, Yan-Hsiu Liu
2025	J	`jnl`	Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition. ACM Trans. Design Autom. Electr. Syst. Po-Wei Chen, Sheng-Tan Huang, Shao-Yun Fang
2025	J	`jnl`	LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao-Chiang Shao, Guan-Yu Chen, Yu-Hsien Lin, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu
2025	A*	`conf`	MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version Substitution. DAC Da-Wei Huang, Shao-Yun Fang
2025	—	`conf`	Paired-Spacing-Constrained Package Routing with Net Ordering Optimization. ASP-DAC Yi-Sian Ciou, Ying-Jie Jiang, Yi-Yu Liu, Shao-Yun Fang, Wen-Hao Liu
2025	—	`conf`	Pin Access-aware Multiple Via Pillar Co-Design for Routability Optimization. ASP-DAC Man-Ling Hong, Ying-Jie Jiang, Shao-Yun Fang
2025	A	`conf`	Refinement Strategies for Any-Angle Package Routing with I/O Alignment Consideration. ICCAD Yu-En Lin, Shao-Yun Fang, Yi-Yu Liu
2025	A*	`conf`	Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain Designs. DAC Yu-Wei Chang, Shao-Yun Fang, Kai-Chuan Yang, Min-Ching Lin
2025	—	`conf`	Via Fabrication with Multi-Row Guiding Templates Using Lamellar DSA. ASP-DAC Yun-Na Tsai, Shao-Yun Fang
2024	A*	`conf`	Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimization. DAC Ying-Jie Jiang, Shao-Yun Fang
2024	J	`jnl`	LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection. CoRR Hao-Chiang Shao, Guan-Yu Chen, Yu-Hsien Lin, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu
2024	A	`conf`	Overview of 2024 CAD contest at ICCAD. ICCAD Shao-Yun Fang, Yi-Yu Liu, Chung-Kuan Cheng, Tsun-Ming Tseng
2024	—	`conf`	Practical Mixed-Cell-Height Legalization Considering Vertical Cell Abutment Constraint. ISPD Teng-Ping Huang, Shao-Yun Fang
2024	A	`conf`	SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture. ICCAD Sheng-Tan Huang, Ying-Jie Jiang, Shao-Yun Fang, Chung-Kuan Cheng
2023	—	`conf`	Advanced Design Methodologies for Directed Self-Assembly. ISPD Shao-Yun Fang
2023	J	`jnl`	COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun-Jhe Jiang, Shao-Yun Fang
2023	—	`conf`	Data-Driven Approaches for Process Simulation and Optical Proximity Correction. ASP-DAC Hao-Chiang Shao, Chia-Wen Lin, Shao-Yun Fang
2023	J	`jnl`	Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Sian Ciou, An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
2023	J	`jnl`	Keeping Deep Lithography Simulators Updated: Global-Local Shape-Based Novelty Detection and Active Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao-Chiang Shao, Hsing-Lei Ping, Kuo-Shiuan Chen, Weng-Tai Su, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu
2023	A*	`conf`	Lamellar DSA-aware Detailed Routing Considering Double Patterning and Short Template Minimization. DAC Kuei-Lin Wu, Shao-Yun Fang
2023	—	`conf`	MIA-Aware Detailed Placement and VT Reassignment for Leakage Power Optimization. ASP-DAC Hung-Chun Lin, Shao-Yun Fang
2023	A	`conf`	Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement. DATE Li-Chen Wang, Shao-Yun Fang
2023	—	`conf`	Pin Access-Oriented Concurrent Detailed Routing. ISPD Yun-Jhe Jiang, Shao-Yun Fang
2023	A	`conf`	Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations. ICCAD Da-Wei Huang, Ying-Jie Jiang, Shao-Yun Fang
2022	A	`conf`	A Robust Quantum Layout Synthesis Algorithm with a Qubit Mapping Checker. ICCAD Tsou-An Wu, Yun-Jhe Jiang, Shao-Yun Fang
2022	J	`jnl`	Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips. ACM Trans. Design Autom. Electr. Syst. Sudip Poddar, Sukanta Bhattacharjee, Shao-Yun Fang, Tsung-Yi Ho, Bhargab B. Bhattacharya
2022	J	`jnl`	Keeping Deep Lithography Simulators Updated: Global-Local Shape-Based Novelty Detection and Active Learning. CoRR Hao-Chiang Shao, Hsing-Lei Ping, Kuo-Shiuan Chen, Weng-Tai Su, Chia-Wen Lin, Shao-Yun Fang, Pin-Yian Tsai, Yan-Hsiu Liu
2022	—	`conf`	SpeedER: A Supervised Encoder-Decoder Driven Engine for Effective Resistance Estimation of Power Delivery Networks. MLCAD Bing-Yue Wu, Shao-Yun Fang, Hsiang-Wen Chang, Peter Wei
2021	J	`jnl`	From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao-Chiang Shao, Chao-Yi Peng, Jun-Rei Wu, Chia-Wen Lin, Shao-Yun Fang, Pin-Yen Tsai, Yan-Hsiu Liu
2021	—	`conf`	Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation. ASP-DAC Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen
2021	J	`jnl`	Manufacturability Enhancement With Dummy via Insertion for DSA-MP Lithography Using Multiple BCP Materials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun-Jhe Jiang, Kuo-Hao Wu, Shao-Yun Fang
2021	J	`jnl`	Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
2021	J	`jnl`	Placement-guided pin layout substitution for routability optimization. Microelectron. J. Jia-Hong Chang, Shao-Yun Fang
2021	—	`conf`	RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection. ISQED Yu-Kai Chuang, Yong Zhong, Yi-Hao Cheng, Bo-Yi Yu, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
2020	A	`conf`	COALA: Concurrently Assigning Wire Segments to Layers for 2D Global Routing. ICCAD Yun-Jhe Jiang, Shao-Yun Fang
2020	—	`conf`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. ASP-DAC Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	J	`jnl`	FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. CoRR Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza
2020	J	`jnl`	From IC Layout to Die Photo: A CNN-Based Data-Driven Approach. CoRR Hao-Chiang Shao, Chao-Yi Peng, Jun-Rei Wu, Chia-Wen Lin, Shao-Yun Fang, Pin-Yen Tsai, Yan-Hsiu Liu
2020	A	`conf`	Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process. ICCAD An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu
2020	—	`conf`	Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. ISPD Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
2020	A	`conf`	Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation. ICCAD Kai-Chuan Yang, Tao-Chun Yu, Shao-Yun Fang, Teng-Yuan Cheng, Yang-Chun Liu, Cindy Chin-Fang Shen
2020	J	`jnl`	Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources. IEEE Trans. Very Large Scale Integr. Syst. Yi-Hao Cheng, Tao-Chun Yu, Shao-Yun Fang
2020	J	`jnl`	Obstacle-Avoiding Open-Net Connector With Precise Shortest Distance Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang
2020	—	`conf`	Stitch-Aware Routing Considering Smart Boundary for Multiple E-Beam Lithography. VLSI-DAT Chih-Hsiang Hsu, Shao-Yun Fang
2020	—	`conf`	Via Pillar-aware Detailed Placement. ISPD Yong Zhong, Tao-Chun Yu, Kai-Chuan Yang, Shao-Yun Fang
2019	—	`conf`	Capacitance Minimization Clock Synthesis with Blockage-Avoiding Hybrid-Structure Network. ISPACS Chun-Wei Ho, Shao-Yun Fang
2019	—	`conf`	Deep learning-based framework for comprehensive mask optimization. ASP-DAC Bo-Yi Yu, Yong Zhong, Shao-Yun Fang, Hung-Fei Kuo
2019	J	`jnl`	Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints. IEEE Trans. Very Large Scale Integr. Syst. Tao-Chun Yu, An-Jie Shih, Shao-Yun Fang
2019	A*	`conf`	Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition. DAC Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
2019	J	`jnl`	Printability Enhancement with Color Balancing for Multiple Patterning Lithography. IEEE Trans. Emerg. Top. Comput. Kuan-Jung Chen, Shao-Yun Fang
2019	A	`conf`	Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. DATE Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
2018	J	`jnl`	Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tao-Chun Yu, Shao-Yun Fang, Chia-Ching Chen, Yulong Sun, Poki Chen
2018	—	`conf`	Flip-chip routing with IO planning considering practical pad assignment constraints. ASP-DAC Tao-Chun Yu, Shao-Yun Fang
2018	—	`conf`	Guiding Template-Induced Design Challenges in DSA-MP Lithography. ISVLSI Shao-Yun Fang, Kuo-Hao Wu
2018	A*	`conf`	Obstacle-avoiding open-net connector with precise shortest distance estimation. DAC Guan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang
2018	A*	`conf`	PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. DAC Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann
2018	J	`jnl`	Provably Good Max-Min- IEEE Trans. Very Large Scale Integr. Syst. Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan
2018	A	`conf`	RouteNet: routability prediction for mixed-size designs using convolutional neural network. ICCAD Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu
2018	—	`conf`	Triple patterning lithography-aware detailed routing ensuring via layer decomposability. VLSI-DAT Hua-Yi Wu, Shao-Yun Fang
2017	J	`jnl`	Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing. IEEE Trans. Very Large Scale Integr. Syst. Shao-Yun Fang, Kuo-Hao Wu
2017	J	`jnl`	Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly. IEEE Trans. Circuits Syst. I Regul. Pap. Kun-Lin Lin, Shao-Yun Fang, Yun-Xiang Hong
2017	—	`conf`	Guiding template-aware routing considering redundant via insertion for directed self-assembly. ASP-DAC Kun-Lin Lin, Shao-Yun Fang
2017	A*	`conf`	Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification. DAC Kuan-Jung Chen, Yu-Kai Chuang, Bo-Yi Yu, Shao-Yun Fang
2017	J	`jnl`	Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yun Fang, Yun-Xiang Hong, Yi-Zhen Lu
2017	A	`conf`	Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithography. ICCAD Kuo-Hao Wu, Shao-Yun Fang
2016	—	`conf`	Design optimization considering guiding template feasibility and redundant via insertion for directed self-assembly. APCCAS Shao-Yun Fang, Yun-Xiang Hong
2016	J	`jnl`	Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
2015	—	`conf`	Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing. ASP-DAC Shao-Yun Fang
2015	A*	`conf`	EUV and e-beam manufacturability: challenges and solutions. DAC Yao-Wen Chang, Ru-Gun Liu, Shao-Yun Fang
2015	—	`conf`	Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. ASP-DAC Shao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang
2015	A	`conf`	Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. ICCAD Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan
2015	A	`conf`	Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly. ICCAD Shao-Yun Fang, Yun-Xiang Hong, Yi-Zhen Lu
2015	J	`jnl`	Stitch-Aware Routing for Multiple E-Beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
2014	J	`jnl`	A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen
2014	A*	`conf`	Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. DAC Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang
2013	J	`jnl`	Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
2013	—	`conf`	Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. ISPD Shao-Yun Fang, Chung-Wei Lin, Guang-Wan Liao, Yao-Wen Chang
2013	A*	`conf`	Stitch-aware routing for multiple e-beam lithography. DAC Shao-Yun Fang, Iou-Jen Liu, Yao-Wen Chang
2012	A*	`conf`	A novel layout decomposition algorithm for triple patterning lithography. DAC Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen
2012	—	`conf`	Graph-based subfield scheduling for electron-beam photomask fabrication. ISPD Shao-Yun Fang, Wei-Yu Chen, Yao-Wen Chang
2012	J	`jnl`	Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Yun Fang, Szu-Yu Chen, Yao-Wen Chang
2012	A*	`conf`	Simultaneous flare level and flare variation minimization with dummification in EUVL. DAC Shao-Yun Fang, Yao-Wen Chang
2010	A	`conf`	Redundant-wires-aware ECO timing and mask cost optimization. ICCAD Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang