Shao-Chun Hung

18 papers A* 2A 7B 1Misc 2Journal 5Unranked 1
YearRankTypeTitle / Venue / Authors
2025 J jnl
Reinforcement-Learning-Based Test Point Insertion for Power-Safe Testing in Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shao-Chun Hung, Arjun Chaudhuri, Krishnendu Chakrabarty
2024 J jnl
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst.
Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty
2024 Misc conf
Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration.
VTS
Shao-Chun Hung, Partho Bhoumik, Krishnendu Chakrabarty
2023 A conf
Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs.
ITC
Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty
2023 Misc conf
Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs
VTS
Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty
2023 B conf
Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning
ETS
Shao-Chun Hung, Arjun Chaudhuri, Krishnendu Chakrabarty
2023 J jnl
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, Krishnendu Chakrabarty
2022 A conf
Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration.
ITC
Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty
2022 A conf
Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs.
DATE
Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty
2022 A conf
Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs.
DATE
Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty
2022 A conf
Observation Point Insertion Using Deep Learning.
ICCAD
Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang
2021 J jnl
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang
2021 A conf
Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits.
DATE
Sanmitra Banerjee, Arjun Chaudhuri, Shao-Chun Hung, Krishnendu Chakrabarty
2021 J jnl
Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty
2020 A conf
Design of a Reliable Power Delivery Network for Monolithic 3D ICs
DATE
Shao-Chun Hung, Krishnendu Chakrabarty
2020 — conf
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs
ATS
Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty
2019 A* conf
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing.
DAC
Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang
2019 A* conf
Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis.
DAC
Hao Chen, Shao-Chun Hung, Jie-Hong R. Jiang